What does <= operator do in this code?

问题:

module counter (clk,rst,enable,count);
input clk, rst, enable;
output [3:0] count;
reg [3:0] count;

always @ (posedge clk or posedge rst)
if (rst) begin
  count <= 0;
end else begin : COUNT
  while (enable) begin
    count <= count + 1;
    disable COUNT;
  end
end

endmodule

(Source: http://www.asic-world.com/verilog/verilog_one_day2.html#While)

From what I have learnt, <= is a relational operator and it will return 1 if true and 0 if false, but where does it return in this code?

回答1:

In the context of your code, <= is not a relational operator, it is an assignment operator. There are two types of assignment in Verilog:

• blocking : =

• non-blocking : <=

In a Verilog design, you

• always use blocking assignments for combinational logic

• always use non_blocking assignments for sequential logic

If you do not, you simulation will be indeterminate - it will not necessarily behave the same way every time you run it. Which, of course, is not good.

So, why is that? Well, to start you must learn that Verilog has 4 scheduling regions:

from prev time step
        |
      ACTIVE
        |
     INACTIVE
        |
       NBA
        |
    POSTPONED
        |
        V
 to next time step

Blocking assignments are executed in the ACTIVE region. However, while the right-hand side of a non-blocking assignment is evaluated in the ACTIVE region, the assignment does not occur until the NBA region. This is key to why you need to use them for sequential logic.

So, why do you need to use non-blocking assignments for sequential logic? The reason is because the delay between evaluation of the right-hand side and assignment of the left hand side enables a Verilog simulation to be determinate, ie to behave the same way every time you run it. This delay means that the behaviour of the simulation does not depend on the order in which the always blocks are executed, which it would if only blocking assignments were used.

A simple analogy to the delay between evaluating the right-hand side of a non-blocking assignment and assigning the left-hand side is the clock-to-Q delay of a real flip-flop. In a real flip-flop, there is always a small delay (clock-to-Q delay) between the D input being sampled (by the clock) and the Q output being driven. This is vital to the correct operation of real sequential logic. For example, if there were no clock-to-Q delay in a real flip-flop instead of it taking exactly 4 clocks for the D input of the first flip-flop in a 4-stage shift register to get to the Q output of the fourth flip-flop, it could take any number of clocks between 1 and 4: its behaviour would also be indeterminate.