Verilog bitwise or (“|”) monadic

2019-06-07 04:43发布

问题:

I've seen Verilog code where the bitwise or operator ("|") is used monadic. What's the purpose?

For example

| address[15:14]==0

or

|address[15:14]? io_din : ramrd

Cann't we omit the "|" in these cases?

回答1:

In this case it acts as a reduction operator, for example:

|4'b1000 => 1'b1 (OR)
&4'b1000 => 1'b0 (AND)
^4'b1000 => 1'b1 (XOR)

|4'b0000 => 1'b0
&4'b1111 => 1'b1
^4'b1111 => 1'b0

ORing the entire bus to a 1 bit value, or applying an AND/XOR to the entire bus.

This is referred to as a 'unary' operator as it only take a right hand argument. They are covered in Section 11.4.9 of SystemVerilog IEEE1800-2012.



回答2:

|address[15:14]? io_din : ramrd

is the shortcut for writing

(address[15] | address[14]) ? io_din : ramrd

i.e bitwise ORing of all bits of the bus together to generate a 1bit value. In this case it will evaluate as HIGH if either(or both) bit 15 OR bit 14 is HIGH.

similarly you can write other bitwise operators

&address[15:14]? io_din : ramrd   // ANDing

^address[15:14]? io_din : ramrd   // XORing


回答3:

In the examples provided, the code with | is functionally equivalent to the same coded with the | omitted. Three possible reason to have and keep the | for the provided code are:

  1. It gives guidance to the synthesizer: first OR the address bits then compare to 0, instead of comparing each address bit to 0 then ANDing the results. It is the same functional result with different gate configurations.
  2. It following a coding style or formatting style requirement.
  3. It just read better (visually/structurally appealing) because there is a |address[15:14]==1 on a near by line of code to |address[15:14]==0. (Reminder: |address[15:14]==1 is not the same as address[15:14]==1)


回答4:

On the specific question of whether the '|' can be omitted in these cases:

Whether |address[15:14] and address[15:14] are identical depends on the context (in general, they aren't, because unknowns are handled differently). Your first example compared to 0, and it's true that the | can be dropped in this particular case, but it wouldn't be true if you compared to anything other than 0.

Your second example is trickier. The LRM doesn't appear to specify how the first expression in a ternary is evaluated. I know of 2 sims that evaluate it as a reduction-OR, so the | can be dropped in those cases. However, if a sim instead evaluates it in the same way as an if (ie if(address[15:14])) then the | is required.

Synthesis is simpler, of course, since the synthesiser doesn't have to worry about unknowns.



标签: verilog