Generate State Machine graph from VHDL code?

问题:

Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers!

回答1:

Active HDL has a feature called "Code2Graphics" which supports this. Additionally, some synthesis tools (typically ones you would have to pay for) also support this.

Note that an RTL view is more commonly available in synthesis tools (such as XST).

回答2:

Modelsim SE (and DE?) have these kind of things. But, not for free :-(