What is the improvement in ARM11 for cache

It's said in ARM11, Cache is physically addressed, solving many cache aliasing problems and reducing context switch overhead

How to understand physically addressed? How does it help to solve the cache aliasing problems and to reduce the context switch overhead?

There are three common types of cache.

VIVT = Virtually Indexed Virtually Tagged
VIPT = Virtually Indexed Physically Tagged
PIPT = Physically Indexed Physically Tagged

there is also

PIVT = Physically Indexed Virtually Tagged

PIPT is usually used for 2nd Level and deeper caches because the physical address has to be known at that moment anyway, but armv7 also introduced PIPT L1 DCaches. PIVT is not really practical and so not used in the real world.

The difference is how the cache lines are connected to the underlying memory.

Virtually Indexed means that the pure cache line lookup is done with the virtual address and so can be done BEFORE any Virtual to Physical address-translation. The tagging then will decide if the cache line really maps to your underlying memory or contains data for some other memory location which happens to map to the same cache line.

If the tagging is done with the virtual address then two processes which happen to use the same virtual address could trip on each other, because one process might access data which the other process put into the cache. So for a VIVT-cached cpu the kernel has to flush the whole cache on a context-switch. So the new process will not access incorrect data by accident, which means in general a context-switch is a VERY expensive operation on VIVT-cached CPUs. On ARMv5 and upwards there is support for so called Fast Context Switch Extensions, which modifies the virtual address with an tag. But that involves a lot of limitations.

In contrast VIPT will still use the virtual address to find the cache line, but then will check the tag against the physical-address, so the MMU lookup can be done in parallel to the cache line lookup.

Aliasing is another big problem with VIVT-caches. Because two virtual addresses might point to the same physical memory location (which might happen when you share memory between user and kernel space). So you could have two locations in your cache with different data, which can be very hard to manage properly (explicitly flushing and invalidating the cache in the right order).