Verilog Always block using (*) symbol

问题:

I have a simple question regarding how to write an always block in a Verilog module.
If I have the following inputs in my Verilog module:

input        [31:0] PCplus4 ;       // Value of PC + 4
input        [31:0] A;          // Value A, i.e. RSbus (Use Forwarded Value)
input        [31:0] B;          // Value B, i.e. RTbus (Use Forwarded Value)
input        [31:0] IMM;            // Extended Immediate Value
input        [25:0] TARGET;         // Target Address for Jumps
input         [3:0] BR;         // Branch Selector Input

Is there any difference if I use

always @ (*)  

instead of

always @ (PCplus4  or A or B or IMM or TARGET or BR)  

Is this always @ (*) syntax valid for all versions of Verilog?

回答1:

The always @(*) syntax was added to the IEEE Verilog Std in 2001. All modern Verilog tools (simulators, synthesis, etc.) support this syntax.

Here is a quote from the LRM (1800-2009):

An incomplete event_expression list of an event control is a common source of bugs in register transfer level (RTL) simulations. The implicit event_expression, @*, is a convenient shorthand that eliminates these problems by adding all nets and variables that are read by the statement (which can be a statement group) of a procedural_timing_ control_statement to the event_expression.

So, your two lines of code may be equivalent (it depends on the code in the body of your always block). However, the @* syntax is easier to maintain.

回答2:

always @(*) was an addition to the language in the 2001 revision of the standard. It is supported by all recent releases of quality tools. I have no concerns about using the construct in code intended for arbitrary reuse, however, there is a possibility of encountering an old tool that does not support always @(*), especially when in-house utilities are involved.

回答3:

It's just a shortcut for listing all of the wires that the always block depends on. Those wires are the "sensitivity list". One advantage of using it is that synthesized code is unlikely to care what you put in the sensitivity list (other than posedge and negedge) because the wires will be "physically" connected together. A simulator might rely on the list to choose which events should cause the block to execute. If you change the block and forget to update the list your simulation might diverge from the actual synthesized behavior.

回答4:

Though both are equivalent, using always@(*) avoids having any simulation-synthesis mismatch. Lets assume you have 15 signals in the sensitivity list as below:

always@( a1 or a2 or ... or a15)

Now assume that the designer has missed having a14 in this list by mistake. The synthesis tool ignores this fact and synthesizes the code assuming all the signals on RHS within this block are in the sensitivity list. Whereas the simulation tool behaves differently since it depends on the sensitivity list.

回答5:

For the 1st question....i would say that depends if in second scenario that those are the only inputs you feel can change which will cause a triggering to the output. Ideally it would be better to use * as it indicates "for any change in inputs", Also it is helpful in avoiding verbose code.

For the second question.....it was introduced in verilog -2001 and ever since then it has been used extensively.

回答6:

* means all the inputs included, so it is equivalent to writing all the inputs. Using the * symbol is also useful with always if you want your module to be combinational circuit not sequential, since there is something always changing whenever any input is changed.