问题:

I am a beginner in VHDL coding. I am trying to implement frequency multiplier using VHDL. I have implemented frequency divider, but frequency multiplier is not that easy. Please give an idea for implementing that.

回答1:

For implementation in a FPGA, you must use a dedicated FPGA resource like Phase-Locked Loop (PLL) (see Altera and Xilinx) or Digital Clock Managers (DCM) (see Xilinx) to multiply a frequency.

These resources can create an output frequency based on an input frequency like:

f_out = (N / M) * f_in

The PLL and DCM resources are device specific, and often very advanced resources, that allows additional control over phase, delay, etc., so take a look at the resources in the device you are using.

回答2:

A clock frequency can be divided using flip-flops. However, clock multiplication cannot be performed by purely digital circuits. As mentioned by Morten, a PLL unit (which is a hybrid circuit, thus not directly implemented with VHDL) is used for that. PLLs are built-in units in FPGAs, so all that you have to do is to instantiate them.

A detailed example on how to do it is in Appendix G of "Circuit Design and Simulation with VHDL", by V. Pedroni. Several complete examples usign PLLs for clock multiplication in data serializers are also included in that book.