Include a module in verilog

问题:

I want to include a verilog module into another file. How do I include it in the code and how do I compile the code to include the header file? Is it like in c?

回答1:

1. A basic example can include them both in the same file as shown on page 4 of verilog in a day.

2. All files in the same folder should be automatically found.

3. Include them as shown in Hello_World_Program_Output or Example below.

4. Advanced workflows can have files.f listing the verilog or config files specifying include directories.

Include example for (3):

`include "folder/sub.sv"
module top;
  sub sub_i(
    .a(),
    .b()
    ...

The file extension .v is used for verilog compilation, your compiler should use the latest standard up to Verilog 2005. The .sv extension is for SystemVerilog. Which replaced Verilog in 2009. The file extension causes the compiler to switch to SystemVerilog.