<= Assignment Operator in Verilog

问题:

What does the <= do in Verilog?

For example:

always @(posedge Clock) begin
   if (Clear) begin
      BCD1 <= 0;
      BCD0 <= 0;
   end
end

回答1:

"<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators.

It is Recommended to use non-blocking assignment for sequential logic and blocking assignment for combinational logic, only then it infers correct hardware logic during synthesis.

Non-blocking statements in sequential block will infer flip flop in actual hardware.

Always remember do not mix blocking and non-blocking in any sequential or combinational block.

During scheduling process of simulator:

There are four regions and order of execution of commands as follows

1) Active region
     --Blocking assignments
     --Evaluation of RHS of non-blocking assignments(NBA)
     --Continuous assignment
     --$display command
     --Evaluate input and output of primitives
2) Inactive region
     --#0 blocking assignments
3) NBA(non-blocking assignment update)
     --update LHS of non-blocking assignments (NBA)
4) Postponed
     --$monitor command
     --$strobe command

Using of blocking assignment "=" for two variable at the same time slot causes race condition

eg: Verilog code with race condition,

always @(posedge Clock) 
   BCD0 = 0; // Usage of blocking statements should be avoided
always @(posedge Clock) 
   BCD1 = BCD0; 

In order to avoid race condition use non-blocking statement "<="

eg:

   always @(posedge Clock) 
       BCD0 <= 0; // Recommended to use NBA
    always @(posedge Clock) 
       BCD1 <= BCD0; 

When this block is executed, there will be two events added to the non blocking assign update queue. Hence, it does the updation of BCD1 from BCD0 at the end of the time step.

Using Non-blocking "<=" assignment in continuous assignment statement is not allowed according to verilog LRM and will result in compilation error.

eg:

assign BCD0 <= BCD1; //Results in compilation error

Only use NBA in procedural assignment statements,

 - initial and
 - always blocks

回答2:

This is called a 'non-blocking' assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables.

For example, in this code, when you're using a non-blocking assignment, its action won't be registered until the next clock cycle. This means that the order of the assignments is irrelevant and will produce the same result.

The other assignment operator, '=', is referred to as a blocking assignment. When '=' assignment is used, for the purposes of logic, the target variable is updated immediately.

The understand this more deeply, please look at this example (from Wikipedia):

module toplevel(clock,reset);
    input clock;
    input reset;

    reg flop1;
    reg flop2;

    always @ (posedge reset or posedge clock)
        if (reset)
        begin
            flop1 <= 0;
            flop2 <= 1;
        end
        else
        begin
            flop1 <= flop2;
            flop2 <= flop1;
        end
endmodule

In this example, flop1 <= flop2 and flop2 <= flop1 would swap the values of these two regs. But if we used blocking assignment, =, this wouldn't happen and the behavior would be wrong.

回答3:

"<=" is a non-blocking assignment operator in verilog."=" is a blocking assignment operator.

Consider the following code..

always@(clk)
begin
a=b;
end

always@(clk)
begin
b=a;
end

The values of a and b are being exchanged using two different always blocks.. Using "=" here caused a race-around condition. ie. both the variables a and b are being changes at the same time.. Using "<=" will avoid the race-around.

always@(clk)
begin
a<=b;
end

always@(clk)
begin
b<=a;
end

Hope i helped too..

回答4:

Since people have already explained the blocking/non blocking situation, I'll just add this here to help with understanding. " <= " replaces the word "gets" as you read code

For example :

.... //Verilog code here

A<=B //read it as A gets B

When does A get B? In the given time slot, think of everything in hardware happening in time slots, like a specific sampled event, driven by clock. If the "<=" operator is used in a module with a clock that operates every 5ns, imagine A getting B at the end of that time slot, after every other "blocking" assignments have resolved and at the same time as other non blocking assignments.

I know its confusing, it gets better as you use and mess up bunch of designs and learn how it works that way.

回答5:

<= is a non blocking assignment. The <= statements execute parallely. Think of a pipelined architecture, where we come across using such assignments.

A small exammple:

// initialise a, b, c with 1, 2 and 3 respectively. initial begin a <= 1 b <= 2 c <= 3 end

always@(clock.posedge) begin a <= b b <= c c <= a end

After the first posedge clock: a = 2, b = 3, c = 1

After the second posedge clock: a = 3, b = 1, c = 2

After third posedge clock: a = 1, b = 2, c = 3

回答6:

** Your question was downvoted because it is something you can easily find in a basic verilog handout or a book. Isnt quite helpful for you or others to be asked on a forum like this.

As most told, it is a "Non Blocking <=" assignment widely used for Sequential logic design because it can emulate it best. Here is why : Mostly involving a delay(here posedge clock) it is something like it schedules the evaluation of the RHS to LHS after the mentioned delay and moves on to the next statement(emulating sequential) in flow unlike "Blocking = " which will actually delay the execution of the next statement in line with the mentioned delay (emulating combinational)