making all rules depend on the Makefile itself

问题:

When I change a Makefile, its rules may have changed, so they should be reevaluated, but make doesn't seem to think so.

Is there any way to say, in a Makefile, that all of its targets, no matter which, depend on the Makefile itself? (Regardless of its name.)

I'm using GNU make.

回答1:

This looks like one more simple, useful, logical thing that Make should be able to do, but isn't.

Here is a workaround. If the clean rule is set up correctly, Make can execute it whenever the makefile has been altered, using an empty dummy file as a marker.

-include dummy

dummy: Makefile
    @touch $@
    @$(MAKE) -s clean

This will work for most targets, that is targets that are actual files and that are removed by clean, and any targets that depend on them. Side-effect targets and some PHONY targets will slip through the net.

回答2:

The only answer I know to this is to add makefile explicitly to the dependencies. For example, %.o: %.c makefile $(CC) $(CFLAGS) -c $<