Ring buffers and DMA

I'm trying to understand everything that happens in between the time a packet reaches the NIC until the time the packet is received by the target application.

Assumption: buffers are big enough to hold an entire packet. [I know it is not always the case, but I don't want to introduce too many technical details]

One option is:

 1. Packet reaches the NIC.
 2. Interrupt is raised.
 2. Packet is transferred from the NIC buffer to OS's memory by means of DMA.
 3. Interrupt is raised and the OS copies the packet from it's buffer to the relevant application.

The problem with the above is when there is a short burst of data and the kernel can't keep with the pace. Another problem is that every packet triggers an interrupt which sounds very inefficient to me.

I know that to solve at least one of the above problems there is a use of several buffers [ring buffer]. However I don't understand the mechanism which will allow to make this works. Suppose that:

 1. Packet arrives to the NIC.
 2. DMA is triggered and the packet is transfered to one of the buffers [from the ring buffer].
 3. Handling of the packet is then scheduled for latter time [bottom half].

Will this work? Is this is what happened in the real NIC driver within the Linux kernel?

According to this slideshare the correct sequence of actions are:

Network Device Receives Frames and these frames are transferred to the DMA ring buffer.
Now After making this transfer an interrupt is raised to let the CPU know that the transfer has been made.
In the interrupt handler routine the CPU transfers the data from the DMA ring buffer to the CPU network input queue for later time.
Bottom Half of the handler routine is to process the packets from the CPU network input queue and pass it to the appropriate layers.

So a slight variant which is followed in this as compared to traditional DMA transfer is regarding the involvement of CPU.

In this we involve CPU after data gets transferred to the DMA ring buffer unlike traditional DMA transfer where we generate the interrupts as soon as data is available and expect CPU to initialise DMA device with appropriate memory locations to make happen the transfer of data.

Read this as well: https://www.safaribooksonline.com/library/view/linux-device-drivers/0596000081/ch13s04.html