VHDL, Can a clocked process introduce latches?

问题:

For example in an unclocked process, all signals have to be set in every case to prevent latches from being implemented. But is this also the matter in a clocked process? I keep thinking this is not the case, but a friend of mine tells me I have to set all signals in all cases to prevent the synthesis from introducing latches even here.

回答1:

A properly implemented clocked process will create registers where an unclocked process would create latches.

And registers are different from latches, especially in our ability to predict their timings; as well as being better supported in FPGAs, so this is usually a Good Thing.

"Properly implemented" means that ONLY Clock and (maybe) Reset) are in the sensitivity list.

回答2:

I was surprised recently because the following code produces latches, even though only clock and reset are on the sensitivity list:

library ieee;
use ieee.std_logic_1164.all;

entity unwanted_latches is
    port (
        clock: in std_logic;
        reset: in std_logic
    );
end;

architecture rtl of unwanted_latches is

    function update_vector(vector: std_logic_vector) return std_logic_vector is
        variable return_value: std_logic_vector(vector'range);
    begin
        return_value := vector;
        return_value(0) := not return_value(0);
        return return_value;
    end;

    signal my_vector: std_logic_vector(7 downto 0) := (others => '0');

begin

    update_my_vector: process (clock, reset) begin
        if reset then
            my_vector <= (others => '0');
        elsif rising_edge(clock) then
            my_vector <= update_vector( my_vector );
        end if;
    end process;

end;

The exact message output by Quartus 12.1 is:

Warning (10631): VHDL Process Statement warning at unwanted_latches.vhd(25): inferring latch(es) for signal or variable "my_vector", which holds its previous value in one or more paths through the process

So, my strict answer to your question would have to be: yes, a clock process can introduce latches. But I'm more inclined to agree with @MartinThompson that this is a tool problem.

回答3:

Sounds like there may be a terminology issue...

• Flipflops are edge-triggered storage elements
• Latches are level-sensitive storage elements

You can't get a latch in a clocked process that's done right - just the clock in the sensitivity list (and if the reset is asynchronous, that too). Any tool which produces latches from that description is broken.

(I guess it's possible that, in olden times, you might get flipflops that you didn't want if you didn't initialise signals that weren't supposed to the made into flipflops, but there's a lot of ancient but wrong "lore" around where VHDL is concerned)