Is it possible to have generic type in vhdl?

问题:

Is there a way in VHDL to have generic types? So for example I want to call a procedure but I'm not sure what type the signal has I want to give as paarameter, is it possible to declare the parameter as generic? Like in C++ you would use a Template.

procedure eq_checker(name : string; sig : ANYTHING); should : ANYTHING; at : time) is
  if (at = now) then
    if sig = should then
      report "has same value" severity note;
    else
      report "has not same value" severity note;
    end if;
  end if;
end checker;

At least it should be possible to use different signal types as "sig".

回答1:

The Peter Ashenden and Jim Lewis book "VHDL-2008 - Just the new stuff" opens with

Chapter 1 : Enhanced Generics
1.1 Generic Types

So, if your tool supports VHDL-2008 properly, you can now declare generic types, and you can declare generics on subprograms (not just entities).

And if they have followed the Ada model, the generics will be checked when you first compile them, not when you instantiate them, so that any instantiation that compiles will work, unlike the situation with C++ templates where bugs can lie dormant for years until you instantiate them in a particular way (because C++ templates are closer to macros than true generic metaprogramming)

Example : untested, but written following examples on p.17 of aforementioned book...

procedure eq_checker
         generic  (type ANYTHING) 
         parameter(name : string; sig,should : ANYTHING; at : time) is
begin
  if (at = now) then
    if sig = should then
      report "has same value" severity note;
    else
      report "has not same value" severity note;
    end if;
  end if;
end procedure eq_checker;

回答2:

if you don't know the type in the very moment you write e.g. a procedure, you can use a subtype. you can always change the subtype before synthesis. ok, this is only "somewhat generic" but still... it could look like that:

PACKAGE generics_pkg IS
-- type definition
subtype data_type is integer;

-- instantiation
COMPONENT generics IS
PORT(
    i: IN data_type;
    ii : in data_type;
    o: OUT std_logic    
);
END COMPONENT;

-- procedure
procedure comp (    signal x,y: in data_type; 
                    signal o: out std_logic);

END PACKAGE generics_pkg;

package body generics_pkg is
procedure comp (    signal x,y: in data_type; 
                    signal o: out std_logic) is
begin
    if x = y then
        o<='1';
        report "same value" severity note;
    else
        o<='0';
        report "not same value" severity note;
    end if;
end procedure comp;