From what I understand, all statements inside a PROCESS is executed sequentially. So what happens to a concurrent signal assignment(<=)? Does it work the same way as sequential assignment (:=) or does it execute after a delta delay?
If it executes after a delta delay, then how can all the statements inside PROCESS be called sequential?
If it executes immediately, then is there any difference between := and <= in a process?
The signal assignment (<=) is performed after all the sequential code in the processes are done executing. This is when all the active processes for that timestep are done.
As an example why this is:
Suppose you have an event that triggers 2 processes. These 2 processes use the same signal, but one of them changes the value of that signal. The simulator is only be able to perform one process at the time due to a sequential simulation model (not to confuse with the concurrent model of vhdl). So if process A is simulated first and A changes the signal, B would have the wrong signal value. Therefore the signal can only be changed after all the triggered processes are done.
The variable assignment (:=) executes immidiatly and can be used to e.g. temporarely store some data inside a process.
Sequential signal assignment (<=), as opposed to sequential variable assignment (:=), sequentially schedules an event one delta delay later for the value of the signal to be updated. You can change the scheduled event by using a sequential signal assignment on the same signal in the same process. Only the last update scheduled on a particular signal will occur. For example:
signal a : std_logic := '1'; --initial value is 1
process(clk)
variable b : std_logic;
begin
--note that the variable assignment operator, :=, can only be used to assign the value of variables, never signals
--Likewise, the signal assignment operator, <=, can only be used to assign the value of signals.
if (clk'event and clk='1') then
b := '0' --b is made '0' right now.
a <= b; --a will be made the current value of b ('0') at time t+delta
a <= '0'; --a will be made '0' at time t+delta (overwrites previous event scheduling for a)
b := '1' --b will be made '1' right now. Any future uses of b will be equivalent to replacing b with '1'
a <= b; --a will be made the current value of b ('1') at time t+delta
a <= not(a); --at time t+delta, a will be inverted. None of the previous assignments to a matter, their scheduled event have been overwritten
--after the end of the process, b does not matter because it cannot be used outside of the process, and gets reset at the start of the process
end if;
end process;
It is also important to note that while sequential processes operate sequentially from a logical perspective in the VHDL, when synthesized, they are really turned into complex concurrent statements connecting flip flops. The entire process runs concurrently as a unit between every clock cycle (processes that don't operate on a clock become pure combinational logic). Signals are the values that are actually stored into the flip flops. Variables are just aliasing to make processes easier to read. They are absorbed into combinational logic after synthesis.
