I've been stuck at this problem for some hours now, and it seems I can't find the solution by searching i.e. didn't find anything here or on Google.
Here's my piece of code:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std;
USE work.arrays.ALL;
ENTITY parallel IS
PORT (clk:IN std_logic; text:IN INT_ARRAY(119 DOWNTO 0); result:OUT INT_MATRIX_2D);
END parallel;
ARCHITECTURE arch OF parallel IS
COMPONENT unit_comparator IS
PORT (letter:IN integer; difference:OUT integer);
END COMPONENT;
SIGNAL temp: INT_MATRIX_2D := (others => (others => 0));
SIGNAL temp_differences: INT_ARRAY(119 DOWNTO 0) := (others => 0);
BEGIN
PROCESS(clk)
BEGIN
IF(rising_edge(clk))THEN
FOR index IN 119 TO 1 LOOP
temp(temp_differences(index))(temp_differences(index - 1)) <=
temp(temp_differences(index))(temp_differences(index - 1)) + 1;
END LOOP;
result <= temp;
END IF;
END PROCESS;
wiring_loop: FOR index IN 119 DOWNTO 0 GENERATE
wiring_unit: unit_comparator PORT MAP (text(index), temp_differences(index));
END GENERATE;
END arch;
You see that "FOR index IN 119 TO 1 LOOP" ?
The compiler gives a "Range 119 to 0 is Null" warning (no doubt the whole thing doesn't work as it should), which I seem to have a problem understanding. If there is an integer assigned to "index" at each step through the loop, how can it become null (and it says it happens at every step!). I need a firm understanding rather than a plain solution to this. (Note: All of the modules and packages used are tested and work properly!)
Thank you!
