My SSE-FPU generates the following NaNs:
- When I do a any basic dual operation like ADDSD, SUBSD, MULSD or DIVSD and one of both operands is a NaN, the result has the sign of the NaN-operand and the lower 51 bits of the mantissa of the result is loaded with the lower 51 bits of the mantissa of the NaN-operand.
- When both operations are NaN, the result is loaded with the sign of the destination-register and the lower 51 bits of the result-mantissa is loaded with the lower 51 bits of the destination-register before the operation. So the associative law doesn't count when doing multiplications on two NaN-operands!
- When I do a SQRTSD on a NaN-value, the result has the sign of the NaN-operand and the lower 51 bits of the result is loaded with the lower 51 bits of the operand.
- When I do a multiplication of infinity with zero or infinity, I always get -NaN as a result (binary representation 0xFFF8000000000000u).
- If any operand is a signalling NaN, the result becomes a quiet NaN if the exception isn't masked.
Is this behaviour determined anywhere in the IEEE-754-standard?
NaN have a sign and a payload, together are called the information contained in the NaN.
The whole point of NaNs is that they are "sticky" (maybe Monadic is a better term?), once we have a NaN in an expression the whole expression evaluate to NaN.
Also NaNs are treated specially when evaluating predicates (like binary relations), for example if a is NaN, then it is not equal to itself.
Point 1
From the IEEE 754:
Propagation of the diagnostic information requires that information
contained in the NaNs be preserved through arithmetic operations and
floating-point format conversions.
Point 2
From the IEEE 754:
Every operation involving one or two input NaNs, none of them signaling,
shall signal no exception but, if a floating-point result is to be delivered,
shall deliver as its result a quiet NaN, which should be one of the input
NaNs.
No floating point operation has ever been associative.
I think you were looking for the term commutative though since associativity requires at least three operands involved.
Point 3
See point 4
Point 4
From IEEE 754:
The invalid operations are
1. Any operation on a signaling NaN (6.2)
2. Addition or subtraction – magnitude subtraction of infinities such as,
(+INFINITY) + (–INFINITY)
3. Multiplication – 0 × INFINITY
4. Division – 0/0 or INFINITY/INFINITY
5. Remainder – x REM y, where y is zero or x is infinite
6. Square root if the operand is less than zero
7. Conversion of a binary floating-point number to an integer or
decimal format when overflow, infinity, or NaN precludes a faithful
representation in that format and this cannot otherwise be signaled
8. Comparison by way of predicates involving < or >, without ?, when
the operands are unordered (5.7, Table 4)
Point 5
From IEEE 754:
Every operation involving a signaling NaN or invalid operation (7.1) shall, if
no trap occurs and if a floating-point result is to be delivered, deliver a quiet
NaN as its result.
Due to its relevance, the IEEE 754 standard can be found here.
