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如何修复的赛灵思ISE警告有关敏感列表?(How to fix Xilinx ISE warning

2019-10-17 17:44发布

我综合我的设计与赛灵思ISE 13.1。 目标设备的Virtex 5.然后,我遇到了这样的警告:

 WARNING:Xst:819 - "F:/FRONT-END/h264/inter/src/eei/eei_mvd.vhd" 
line 539: One or more signals are missing in the process sensitivity list. 
To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. 
Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:    
<mvd_l0<3><3>>, <mvd_l0<3><2>>, <mvd_l0<3><1>>, <mvd_l0<3><0>>, <mvd_l0<2><3>>, <mvd_l0<2><2>>,
 <mvd_l0<2><1>>, <mvd_l0<2><0>>, <mvd_l0<1><3>>, <mvd_l0<1><2>>, <mvd_l0<1><1>>, <mvd_l0<1><0>>,
 <mvd_l0<0><3>>, <mvd_l0<0><2>>, <mvd_l0<0><1>>, <mvd_l0<0><0>>, <mvd_l1<3><3>>, <mvd_l1<3><2>>,
 <mvd_l1<3><1>>, <mvd_l1<3><0>>, <mvd_l1<2><3>>, <mvd_l1<2><2>>, <mvd_l1<2><1>>, <mvd_l1<2><0>>,
 <mvd_l1<1><3>>, <mvd_l1<1><2>>, <mvd_l1<1><1>>, <mvd_l1<1><0>>, <mvd_l1<0><3>>, <mvd_l1<0><2>>, 
<mvd_l1<0><1>>, <mvd_l1<0><0>>, <mvd<0>>, <mvd<1>>

下面是我的源代码:

proc_update_next: process(mvd_l0, mvd_l1, mvd, subMBPart_Idx, MBPart_Idx, eei_info )
  begin
    --// Init
    next_mvd_l0 <= mvd_l0;
    next_mvd_l1 <= mvd_l1;
    --// Change
    if eei_info.mb_type =  BLK_8x8 then
      for  i in 3 downto 0 loop
        for  j  in 3 downto 0  loop
          if i = to_integer(unsigned(MBPart_Idx))  and j = to_integer(unsigned(subMBPart_Idx)) then
            next_mvd_l0(i)(j)  <=  mvd(0);
            next_mvd_l1(i)(j)  <=  mvd(1);
          end  if;
        end  loop;
      end loop;
    else
      for  i in 3 downto 0 loop
        if i = to_integer(unsigned(MBPart_Idx)) then
          next_mvd_l0(i)(0)  <=  mvd(0);
          next_mvd_l1(i)(0)  <=  mvd(1);
        end  if;
      end loop;
    end if;
  end process;

更新:我改变我的代码,这样的警告一点点,还是。

的mvd_l0和​​mvd_l1是二维阵列和它出现灵敏度列表上。 我知道我的源代码过于抽象和ISE可能无法理解。

我的Virtex 7(在实验室不缴费)试过那么有没有错误。 所以,我的问题是如何解决这一问题的警告? 我不能无视这样的警告,因为它可以导致锁存器。

Answer 1:

使用VHDL-2008的构建process(all)告诉工具,你想要的敏感性列表包括读取的所有信号。

另外,使它成为一个计时过程中,只对时钟敏感,那么你不必担心任何。



Answer 2:

你只需要设置类似的信号next_mvd_l0next_mvd_l1一组条件一次。 该“初始化”部分仍然是一个问题。 它可能会更好,如果你避开正在重置的过程中使用局部变量。

最佳选择:增加一个复位到敏感列表,如果它的启用,设置next_mvd_ *您初始化值

--// Init
if (reset = '1') then
    next_mvd_l0 <= mvd_l0;
    next_mvd_l1 <= mvd_l1;
end if;

第二个选项:使用局部变量

proc_update_next: process(mvd_l0, mvd_l1, mvd, subMBPart_Idx, MBPart_Idx, eei_info )
    variable mvd_10_local : 2dArrayType;
    variable mvd_11_local : 2dArrayType;
begin
    --// Init
    mvd_10_local := mvd_l0;
    mvd_11_local := mvd_l1;
    --// Change
    if eei_info.mb_type =  BLK_8x8 then
        for  i in 3 downto 0 loop
            for  j  in 3 downto 0  loop
                if i = to_integer(unsigned(MBPart_Idx))  and j = to_integer(unsigned(subMBPart_Idx)) then
                    mvd_10_local(i)(j)  :=  mvd(0);
                    mvd_11_local(i)(j)  :=  mvd(1);
                end  if;
            end  loop;
        end loop;
    else
        for  i in 3 downto 0 loop
            if i = to_integer(unsigned(MBPart_Idx)) then
                    mvd_10_local(i)(j)  :=  mvd(0);
                    mvd_11_local(i)(j)  :=  mvd(1);
            end  if;
        end loop;
    end if;
    next_mvd_l0 <= mvd_10_local;
    next_mvd_l1 <= mvd_l1_local;
end process;


Answer 3:

您可以使用VHDL记录结构(eei_info.mb_type)。 您可以记录每个元素添加到SENS-列表,以XST快乐。 我不理会这个警告。



文章来源: How to fix Xilinx ISE warning about sensitivity list?