我想要实现的K&R算法汉明权重计算256位向量的。 我写我的代码的VHDL为:
entity counter_loop is
Port ( dataIn : in STD_LOGIC_VECTOR (255 downto 0);
dataOut : out STD_LOGIC_VECTOR (8 downto 0);
threshold : in STD_LOGIC_VECTOR (8 downto 0);
clk : in STD_LOGIC;
flag : out STD_LOGIC);
end counter_loop;
architecture Behavioral of counter_loop is
signal val : STD_LOGIC_VECTOR (255 downto 0) := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
begin
process (clk)
variable count : STD_LOGIC_VECTOR (8 downto 0):= "000000000";
begin
flag <= '0';
val <= dataIn;
--if(clk'event and clk = '1') then
while (val > 0) loop
count := count+1;
val <= (val and (val-1));
if (count > threshold) then
flag <= '1';
end if;
end loop;
dataOut <= count;
--end if;
end process;
end Behavioral;
但是,尽管采用Xilinx合成它,在错误出现如
53号线:非静态循环超出限制
任何线索请?
PS:行53是 - 而(值> 0)循环