I am getting the following error running make
:
Makefile:168: *** missing separator. Stop.
What is causing this?
I am getting the following error running make
:
Makefile:168: *** missing separator. Stop.
What is causing this?
As indicated in the online manual, the most common cause for that error is that lines are indented with whitespaces when make
expects tab characters.
target: \\tcmd
where \\t is TAB
target: cmd
Just for grins, and in case somebody else runs into a similar error:
I got the infamous \"missing separator\" error because I had invoked a rule defining a function as
($eval $(call function,args))
rather than
$(eval $(call function,args))
i.e. ($eval $(call...
rather than $(eval $(call...
.
This is a syntax error in your Makefile. It\'s quite hard to be more specific than that, without seeing the file itself, or relevant portion(s) thereof.
For me, the problem was that I had some end-of-line # ...
comments embedded within a define ... endef
multi-line variable definition. Removing the comments made the problem go away.
My error was on a variable declaration line with a multi-line extension. I have a trailing space after the \"\\\" which made that an invalid line continuation.
MY_VAR = \\
val1 \\ <-- 0x20 there caused the error.
val2
In my case error caused next. I\'ve tried to execute commands globally i.e outside of any target.
UPD. To run command globally one must be properly formed. For example command
ln -sf ../../user/curl/$SRC_NAME ./$SRC_NAME
would become:
$(shell ln -sf ../../user/curl/$(SRC_NAME) ./$(SRC_NAME))
In my case, this error was caused by the lack of a mere space. I had this if block in my makefile:
if($(METHOD),opt)
CFLAGS=
endif
which should have been:
if ($(METHOD),opt)
CFLAGS=
endif
with a space after if.
So apparently, all I needed was the \"build-essential\" package, then to run autoconf
first, which made the Makefile.pre.in
, then the ./configure
then the make
which works perfectly...
In my case, the same error was caused because colon:
was missing at end as in staging.deploy:
. So note that it can be easy syntax mistake.
Following Makefile code worked:
obj-m = hello.o
all:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
clean:
$(MAKE) -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean