VHDL equivalent for Verilog @(posedge clk) [closed

问题:

I am not familiar with verilog. I did my best trying to convert it.

While simulating the clock is going from '0' to 'x' which is weird. I am suspecting this part to be the problem

repeat(9) @(posedge clk);
   DataIn_i <= 1'b1;
   DataIn_q <= 1'b1;
@(posedge clk);
  FillSel <= 1'b0;
  DataIn_i <= 1'b0;
  DataIn_q <= 1'b0;

here are links to both benches.

Verilog bench - http://a.pomf.se/fvamqd.v Vhdl bench - http://a.pomf.se/riolvf.vhd

any input is welcome,thanks in advance.

EDIT: Can anyone please explain the verilog code given above?

回答1:

Translating Verilog's @posedge clk) to VHDL depends on where it is located in an always or initial block. If it's the very first construct of the block, you can do

Verilog:

always @(posedge signal)
begin
...
end

VHDL:

process(signal)
begin
  if rising_edge(signal) then  -- Older VHDL if (signal'event and signal = '1')
  ...
  end if;
end process;

When embedded in the block, use the wait until statement:

Verilog: @(posedge clk);
VHDL:    wait until rising_edge(signal);

Verilog:  forever ...
VHDL:     loop ... end loop

Verilog: repeat(n) ...
VHDL:    for i in 1 to n loop ... end loop;

Note that when I write ... for Verilog, that is for the single statement that follows, or a single begin/end block that follows.