Can someone explain what would be the reason of this abort. I could not find an explanation in the manual.
Basically I am getting this error in the IFSC code - Synchronous external abort on translation table walk.
The IFSC are bits in the HSR register which is used with an ARMv7A using the virtualization extensions.
The IFSC is basically a virtualization version of the IFSR.
IFSC code - Synchronous external abort on translation table walk.
This means that the CPU had difficulty accessing the page tables. So your code may have jumped to some unmapped address. The first level MMU entry may contain an invalid entry or it contains a 2nd level page table address that gives a bus error when accessed. Basically, it means that something in the page tables did not map well when your faulting instruction executed. You need to inspect the faulting code and then manually walk your page tables to find the actual source of the errors.
If you recently change the table base, some code may execute from the TLB cache and then on the first actual walk, a fault like this will occur.
You probably need to give more information on the context of where the IFSC is read for more help.
