Signal x cannot be synthesized, bad synchrononous

问题:

I'm very new to vhdl and i cannot manage to find what's causing this error. I'm trying to replicate the functionality of a CD54/74HC192 Circuit.

Any help would be greatly appreciated.

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity upg1 is
    Port ( clock_up : in  std_logic;
           clock_down : in  std_logic;
           reset : in  STD_LOGIC;
           asyn_load : in  STD_LOGIC;
           bcd_in : in  STD_LOGIC_VECTOR (3 downto 0);
           bcd_ut : out  STD_LOGIC_VECTOR (3 downto 0);
           term_up : out  STD_LOGIC;
           term_down : out  STD_LOGIC);
end upg1;

architecture Behavioral of upg1 is
subtype state_type is integer range 0 to 15;
signal next_state, present_state: state_type;
signal clock : std_logic;

begin

process(clock_up, clock_down)
begin
   if clock_up = '1' then
      clock <= clock_down;
    else
      if clock_down = '1' then
      clock <= clock_up;
   end if;
   end if;
end process;


process(present_state, asyn_load, clock) -- line 65
begin
   if reset= '1' then
      next_state <= 0;
   end if;
   if (asyn_load = '1' and (rising_edge(clock))) then
         if present_state = 9 or present_state = 13 or present_state = 15 then
         present_state <= 0;
         elsif
         present_state = 10 or present_state = 12 or present_state = 14 then
         present_state <= 9;
         elsif
         present_state = 11 then
         present_state <= 4;
         else
         present_state <= present_state + 1;
         end if;

       else
         if rising_edge(clock) then 
            if present_state = 12 then
            present_state <= 3;
            elsif present_state = 13 then
            present_state <= 4;
            elsif present_state = 14 then
            present_state <= 5;
            elsif present_state = 15 then
            present_state <= 6;
            elsif present_state = 0 then
            present_state <= 9;
            else
            present_state <= present_state - 1;
            end if;
     else
      present_state <= TO_INTEGER(UNSIGNED(bcd_in));
   end if; 
   end if;

end process;
end Behavioral;

I've tried different methods in resolving the error but unable to do so.

Error-console:

line 65: Signal present_state cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.)

回答1:

First, don't use both packages numeric_std and std_logic_arith/unsigned, but use only numeric_std since this is a VHDL standard package, where std_logic_arith/unsigned are Synopsys proprietary. So change to:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

About the real issue, then create state in VHDL through flip-flops using a structure like:

process(clock, reset)
begin
  if rising_edge(clock) then
    ...
  end if;
  if reset = '1' then
    ...
  end if;
end if;

Synthesis will recognize this and infer flip-flops. The reset and clock should not be used elsewhere inside the process.