Syntax error near “generate” and “endgenerate” in

I am new in Verilog and I am trying to implement single precision floating point addition-subtraction using verilog. I am getting an error which I am unable to correct. Can anyone please help me?

module addModule(Rs,Re,Rm,As,Ae,Am,Bs,Be,Bm);

//Declarations of ports
  Rs,Re,Rm;
  As,Bs;
  input [7:0] Ae,Be;
  input [22:0] Am,Bm;

reg [7:0] Re;
reg [22:0] Rm;
reg Rs;
//wire declarations.
wire [23:-1] C;
assign C[-1] = 0;
wire [23:1] sum;
//variable declaration.
genvar count;

always @(*)
begin
//Add two mantissas.
if ((As^Bs)==0)
    begin
        generate   //getting error here "Syntax error near "generate"."
        for(count=0;count<24;count=count+1)
            begin
                add add_1(.c_out(C[count]),.sum(sum[count]),.in1(tempAm[count]),.in2(tempBm[count]),.c_in(C[count-1]));
            end
        endgenerate   //syntax error near "endgenerate"
    end

else
    begin
        generate   //Syntax error near "generate".
        for(count=0;count<24;count=count+1)
            begin
                subtract sub_1(.c_out(C[count]),.dif(sum[count]),.in1(tempAm[count]),.in2(tempBm[count]),.c_in(C[count]));
            end
        endgenerate   //Syntax error near "endgenerate".
    end


end
endmodule

Thanks in advance. :)

In Verilog, when you are instantiating a module, that means you are adding extra hardware to the board.

This hardware must be added before simulation starts(i.e. at compile time). Here, you can not add/remove hardware at each clock pulse.

Once instantiated, the module is executed/checked for each timestamp of simulation, till the end.

So to execute any module, just instantiate it, providing the clk and other required inputs to it, and add the always block in the sub-module itself.

Once the hardware is instantiated, it shall be executed according to the logic inside it, for entire life time.

Here you are instantiating module at wrong place. The use of generate block must be done outside any procedural blocks.

// generate outside any other blocks
   generate   
    for(count=0;count<24;count=count+1)
        begin
            add add_1(.c_out(C[count]),.sum(sum[count]),.in1(tempAm[count]),.in2(tempBm[count]),.c_in(C[count-1]));
        end
    endgenerate

always @(*)
begin
// Other stuff here.
end

If you want to manipulate input signals of the subtract sub_1 module, simply manipulate C,sum and other variables declared in addModule module. Since they are connected, the change shall reflect in subtract sub_1 module too.

For more information on generate block, refer Module Instantiation, Generate block example and a similar question links.