This statement:
reg [7:0] register_file [3:0] = 0;
Produces this error:
Error (10673): SystemVerilog error at simpleprocessor.v(27): assignments to unpacked arrays must be aggregate expressions
First of all I am using Verilog, not SystemVerilog, so why is it giving me a SystemVerilog error?
Second of all, what is the cause of this error, and how can I fix it? I am using it in my desgin of a very rudementary processor to represent the internal working registers as a multidemmnsional array of memory.
It would be such that my registers are accessible directly from the instructions. For example this line:
register_file[instruction[5:4]] <= register_file[instruction[3:2]] + register_file[instruction[1:0]];
But it's not working. Any ideas?
From the SystemVerilog LRM:
The term packed array is used to refer to the dimensions declared before the data identifier name. The term unpacked array is used to refer to the dimensions declared after the data identifier name.
bit [7:0] c1; // packed array of scalar bit types
real u [7:0]; // unpacked array of real types
You have declared an unpacked array, therefore you cannot assign it to a value, hence the error message. With an unpacked array you have to use an aggregate expression to assign the entire array:
logic [7:0] register_file [3:0] = {8'b0, 8'b0, 8'b0, 8'b0};
If you declare a packed array you can then assign as though it was a flat vector:
logic [7:0][3:0] register_file = '0;
You have implied a memory but not specified the location to be set to 0.
You can use an aggregate expressions to define all the values in one line:
reg [7:0] register_file [3:0] = {8'b0, 8'b0, 8'b0, 8'b0};
If it is for an fpga you could also use initial:
reg [7:0] register_file [3:0];
initial begin
for(int i=0; i<4; i++) begin
register_file[i] = 8'b0
end
end
In this instant the loop can be statically unrolled, and therefore is synthesisable.
NB Verilog is depreciated. The Verilog standard has been merged with SystemVerilog in 2009, SystemVerilog 2012 being the latest version.
