I am trying to write a top verilog with instansiations of a few identical modules. the first instansiation should be connected outside, while the other instansiations should be floating. Can anyone help me use the AUTO's with AUTO_TEMPLATE to have emacs connect all inputs to zero, and leave all outputs empty []. I don't have any identification in the module IO name indicating if its input or output (so I can't use wildcards) Is there a way that the tool can identify all inputs (and connect to zero) and all outputs (and leave floating) by itself? Thanks
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问题:
回答1:
I'v managed to have such modules instantiated by using the auto_template with lisp:
/* module_name AUTO_TEMPLATE ( .(.*) (@"(if (equal vl-dir \"output\") \"\" (concat vl-width \"'b0\"))"), );
*/ that way - all inputs are 0, and outputs are left unconnected!!