I am trying to copy a 2d array into another like so:
reg [11:0] input_matrix [0:array_width - 1] [0:array_height - 1];
reg [11:0] output_matrix [0:array_width - 1] [0:array_height - 1];
always @(posedge clk)
begin
if(<some condition>)
output_matrix <= input_matrix;
end
So, we have two 2D arrays of 12-bit values. I'd like to copy one into the other.
This doesn't seem to be possible. Does anyone know the correct way to do this? Or, if not, explain why it's not possible? I can't see any reason why this assignment wouldn't be able to synthesize.
For loops generally don't synthesize well, for obvious reasons. However, is this one of the cases that a for loop can be used, because the loop is statically defined?
As @toolic has mentioned for loops are synthesizable. This is the case were it is perfectly fine as it can be statically unrolled.
The inner loop may not be necessary but I find some version of synthesis tools struggled with memory (array) assignments, they worked but renamed the buses badly which can cause issues with ECO's.
reg [11:0] input_matrix [0:array_width - 1] [0:array_height - 1];
reg [11:0] output_matrix [0:array_width - 1] [0:array_height - 1];
integer i;
integer j;
always @(posedge clk) begin
if(<some condition>) begin
for (i=0; i<array_width; i=i+1 ) begin
for (j=0; j<array_height; j=j+1 ) begin
output_matrix[i][j] <= input_matrix[i][j];
end
end
end
end
The code as you wrote it is synthesizable. See section 2.5.2 in this paper:
http://www.lcdm-eng.com/papers/snug13_SNUG-SV-2013_Synthesizable-SystemVerilog_paper.pdf
