Undefined relational operator for two objects of t

问题:

I currently have a project in VHDL to make a simple vending machine. I have a std_logic signal to determine if the cash in is greater than or equal to the price of the item. The cost is an unsigned constant and the cash is an unsigned signal, but despite them both being unsigned numbers of equal bit length, it tells me the >= operator is undefined. I've looked in multiple reference guides, and all I can find is that the two arguments must be the same type (which they are...) so I'm not sure why it's throwing this error

I have included the proper numeric_std library.

type STATE_TYPE is (RDY, CLCT, VND);
signal state : STATE_TYPE;
signal next_state : STATE_TYPE;

signal cash : unsigned (7 downto 0);
signal cashnew : unsigned (7 downto 0);

signal candy : std_logic;
signal candy_vend : std_logic;
constant cost_candy : unsigned := to_unsigned(60, 8);

signal chips : std_logic;
signal chips_vend : std_logic;
constant cost_chips : unsigned := to_unsigned(50, 8);

begin

candy <= candy1 or candy2 or candy3;
chips <= chip1 or chip2;

candy_vend <= candy and (cash >= cost_candy);
chips_vend <= chips and (cash >= cost_chips);

回答1:

As in other languages, VHDL has a boolean type. It is a integral type and provided in package std.standard. Thus this type is always visible, because this package is referenced by default.

Also like in other languages, a relational operator results in a boolean value. Neither the integral type bit nor the digital logic type std_logic is a boolean. Boolean has values true and false, where as bit has 0 and 1. The std_logic type supports 9 values (9-valued logic, including e.g. error values).

Most operators are defined to accept the right and left operands of the same type, while returning that type again.

So you need to convert your expression at some point back to std_logic, because candy_vend is expecting that type.

Solution 1:

candy_vend <= candy and ('1' when (cash >= cost_candy) else '0');

Solution 2:

candy_vend <= '1' when ((candy = '1') and (cash >= cost_candy)) else '0';

Solution 3:

function to_sl(value : boolean) return std_logic is
begin
  if value then
    return '1';
  else
    return '0';
  end if;
 end function;

Usage:

 candy_vend <= candy and to_sl(cash >= cost_candy);
 candy_vend <= to_sl((candy = '1') and (cash >= cost_candy));