VHDL- use of variables

I am a newbie in VHDL. This is a code for division.

  library ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_unsigned.all;
    use IEEE.numeric_std.all;

entity division3 is
  port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));
  end division3;

  architecture arch_div3 of division3 is
    variable n_times: integer:=1;
             signal v_TEST_VARIABLE1 : integer;
             signal v_TEST_VARIABLE2 : integer;
                   begin 
      P3: PROCESS(num1, num2)
      begin

        if(num1>num2) then
       v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ; 
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L1:loop
         n_times := n_times + 1;
        exit when (v_TEST_VARIABLE2 -  v_TEST_VARIABLE1)>0
        v_TEST_VARIABLE1 <= v_TEST_VARIABLE1 - v_TEST_VARIABLE2;
       end loop L1;


    quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));

   elsif (num2>num1) then
      v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ;  
       v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ;
       L2:loop
        n_times:=n_times+1;
       exit when (v_TEST_VARIABLE1 -  v_TEST_VARIABLE2)>0
       v_TEST_VARIABLE2 <= v_TEST_VARIABLE2 - v_TEST_VARIABLE1;

   quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length));


    else
      quotient <= x"0001";
    end if;

  end PROCESS P3;
    end arch_div3;

I am facing errors on compilation.

** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(25): Physical unit hidden by declaration of 'v_test_variable1' at line 13.
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(25): near "<=": expecting ';'
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(37): Physical unit hidden by declaration of 'v_test_variable2' at line 14.
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(37): near "<=": expecting ';'
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(42): near "else": expecting "END"
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(12): Variable declaration 'n_times' not allowed in this region.
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(47): VHDL Compiler exiting

I am not very clear with the use of signal and variable very well. i think that is where I am messing up. Can someone help me out? Thanks in advance. The testbench for the same code -

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.numeric_std.all;


ENTITY division3_tb IS 
END division3_tb;

ARCHITECTURE behavior OF division3_tb IS

    COMPONENT test  --'test' is the name of the module needed to be tested.

    port(num1, num2 : in std_logic_vector(7 DOWNTO 0);
    quotient : out std_logic_vector(15 DOWNTO 0));

    END COMPONENT;

   signal num1 : std_logic_vector := "00000000";
   signal num2 : std_logic_vector := "00000000";

   signal quotient : std_logic_vector(15 downto 0);

   constant clk_period : time := 1 ns;
BEGIN

   uut: test PORT MAP (
         num1 => num1,
          num2 => num2,
          quotient => quotient
        );       


   clk_process :process
   begin
        num1 <= "00001000";
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        num1 <= "00001110";
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;

  stim_proc: process
   begin         
        wait for 7 ns;
        num2 <="00000001";
        wait for 3 ns;
        num2 <="00000010";
        wait for 17 ns;
        num2 <= "00000011";
        wait for 1 ns;
        num2 <= "00000110";
        wait;
  end process;

END;

It says that:

** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(19): Array type for 'num1' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(20): Array type for 'num2' is not constrained.
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(55): VHDL Compiler exiting

on compilation. how do i instantiate in the test bench?

The Error: ...: Physical unit hidden by declaration of ... is due to lacking ; in the end of the exit when ... statement, whereby the code is interpreted as:

exit when ... > 0 v_TEST_VARIABLE1 ...

So the expression looks like a physical value with unit v_TEST_VARIABLE1, thus the error message.

Some other VHDL related comments to the code:

end loop L2; is missing before quotient <=.
Use only IEEE.numeric_std and not ieee.std_logic_unsigned, since ieee.std_logic_unsigned is not a VHDL IEEE standard package.
The variable n_times should be declared in the process, and not in the architecture, since the variable use is local to the process, and (shared) variables declared in the architecture are generally for test bench use.
The process variable n_times must be initialized in the start of the process, for the initialization to take effect in each calculation. Initial value in declaration only applies to first process run.
Assign to signals v_TEST_VARIABLE1 and v_TEST_VARIABLE2 with <= will not take effect until after a delta cycle, so the new value is not available during the iteration, which looks like the intention in the code. Change the v_TEST_VARIABLE1 and v_TEST_VARIABLE2 to process variables, and use := for assign.
The construction with loop .. exit when ... end loop is not synthesizable, since the exit condition depends on run time values, thus can't be determined at synthesis time for creation of the circuit. Consider changing the algorithm to use a fixed number of loops with for ....
Remember to make a test bench to test the correctness of the algorithm. That will also allow you to optimize the code, with easy test of the updated code.