通用记录（通过VHDL 2008年通用包未遂）(Generic Records (attempted

我想写的组件库C ，该组件在内部分成两个supcomponents c1和c2 ，这是由仿制药配置。该子模块应该由一个记录，那要看仿制药进行连接。该记录也应该在组件中使用。通常我会实例化一个记录package ，并在子组件和组件文件中的文件使用的包。既然是普通的我想用一个通用的软件包（VHDL-2008）可能会提供一个解决方案。

问题是，我需要从子内还访问记录。要做到这一点，我需要use thePackage ，但是用一个通用的包我需要通过初始值（据我所知）。

所以我想（注：荫不会记录在这里工作，我只是想从一个普通的成分，我在那里参数（）的封装组件的参数可以访问一个通用的包？）：

entity genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
end entity;

architecture behav of genericPackagePart is
    package test is new work.genericPackage
    generic map(
        genSize => outputValue
    );

    use work.test.all;
begin
    result <= dummy;  -- dummy is a constant from genericPackage set to the value genSize (generic parameter)
end architecture;

不过，我得到的ModelSim以下错误：

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(17): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(17): Unknown expanded name.
** Error: genericPackagePart.vhd(19): (vcom-1136) Unknown identifier "dummy".
** Error: genericPackagePart.vhd(20): VHDL Compiler exiting

更新：我试过包裹genericPackagePart在一个通用的包，并以实例化genericPackage从包仿制药中，这也不能工作。

流动本来：

测试平台=>实例化genericPackagePart和genericPackage与通用参数
该记录可从测试平台genericPackage
内部genericPackagePart genericPackage进行实例化传递给参数genericPackagePart
该记录可里面genericPackagePart

的ModelSim了错误（ test是我给的参数化实例的名称genericPackage在genericPackagePart ，这是从编译genericPackagePart ）：

** Error: (vcom-11) Could not find work.test.
** Error: genericPackagePart.vhd(11): (vcom-1195) Cannot find expanded name "work.test".
** Error: genericPackagePart.vhd(11): Unknown expanded name.
** Error: genericPackagePart.vhd(13): near "entity": expecting END

我看着传递泛型记录端口类型，但不解决包实例的基础上仿制药的问题

对于completness这里是封装和测试平台：

包：

package genericPackage is
    generic(genSize : integer := 1);

    constant dummy : integer := genSize;
end package;

试验台：

package myGenericPackage is new work.genericPackage
generic map(
    genSize => 5
);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal : integer;
    signal testsignal2 : integer;
    signal dummy : integer := 12;

    component genericPackagePart is
    generic(
        outputValue : integer
    );
    port(
        result: out integer
    );
    end component;
begin
    test : process is
    begin
        wait for 20 ns;
        testsignal <= dummy;
        wait for 20 ns;
        testsignal <= work.myGenericPackage.dummy;
        wait;
    end process;

    testPart: genericPackagePart
        port map(result => testsignal2)
        generic map(outputValue => 128);
end architecture;

我认为，问题是，你的包test需要在实体方面，而不是建筑面积来定义：

package genericPackage is
    generic(genSize : integer := 1);
    constant dummy : integer := genSize;
end package;
entity genericPackagePart is
    generic(outputValue : integer);
    port(result : out integer);

    -- *** Generic package instantiated here ***
    package test is new work.genericPackage
       generic map(genSize => outputValue);

end entity;
architecture behav of genericPackagePart is
    use test.all;
begin
    result <= dummy;  -- dummy is from genericPackage (=genSize)
end architecture;

以下是我测试过它（根据你的测试平台）：

package myGenericPackage is new work.genericPackage
   generic map(genSize => 5);

use work.myGenericPackage.all;

entity genericPackageTestbench is
end entity;

architecture testbench of genericPackageTestbench is
    signal testsignal  : integer;
    signal testsignal2 : integer;
begin
    test : process is
    begin
        testsignal <= work.myGenericPackage.dummy;
        wait for 20 ns;

        assert testsignal = work.myGenericPackage.dummy 
            report "test signal should be work.myGenericPackage.dummy" 
            severity error;
        assert testsignal2 = 128 report "testsignal2 /= 128" severity error;
        report "testsignal = " & integer'image(testsignal);
        report "testsignal2 = " & integer'image(testsignal2);
        report "Finished";
        wait;
    end process;

    testPart : entity work.genericPackagePart
        generic map(outputValue => 128)
        port map(result         => testsignal2);
end architecture;

编译和10.2的ModelSim仿真：

vcom -2008 genpacktest.vhd; vsim -c genericPackageTestbench -do "run -all; quit"

其中报道：

# Loading std.standard
# Loading work.genericpackage
# Loading work.mygenericpackage
# Loading work.genericpackagetestbench(testbench)
# Loading work.genericpackagepart(behav)
# run -all 
# ** Note: Finished
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal = 5
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
# ** Note: testsignal2 = 128
#    Time: 20 ns  Iteration: 0  Instance: /genericpackagetestbench
#  quit