vhdl: Xilinx code error

问题:

We get this error set:

Line 23: Mismatch in number of elements assigned in conditional signal assignment
Line 23: Expression has 1 elements ; expected 7

With this code, line 23 is

Q_out <= "1111110" when Q_in = "0000" else


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder is
Port (
      Q_in  : in  UNSIGNED (3 downto 0);
      Q_out : out  UNSIGNED (6 downto 0)
);
end decoder;
architecture behavioral      of decoder is
begin
Q_out <= "1111110" when Q_in = "0000" else
        "0110000" when Q_in = "0001" else
        "1101101" when Q_in = "0010" else
        "1111001" when Q_in = "0011" else
        "0110011" when Q_in = "0100" else
        "1011011" when Q_in = "0101" else
        "0011111" when Q_in = "0110" else
        "1110000" when Q_in = "0111" else
        "1111111" when Q_in = "1000" else
        "1110011" when Q_in = "1001" else 
        "X";


 end behavioral    ;

回答1:

VHDL is strongly typed, meaning that when you assign signals you need to match port widths and types. In your case, you did not match port widths, which is what the error is telling you. You are trying to assign something that is 1 bit wide to something that is 7 bits wide. Try:

 "1110011" when Q_in = "1001" else 
 (others => 'X');

The others keyword in VHDL means that it will fill up as many X's are needed to match port widths appropriately.