VHDL: Zero-Extend a fixed signal value

问题:

How do you zero-extend a fixed signal value?

I have the following signal:

signal shamt: std_logic_vector(4 downto 0);

Before I assign it to another variable that is of size 31 downto 0 I have to zero extend shamt. I have the following code but I am unsure if it is correct.

muxSOut <= conv_std_logic_vector(unsigned(shamt),32) when (muxSSel = '0') else A;

I'm skeptical about the part conv_std_logic_vector(unsigned(shamt), 32).

Will this extend shamt, which is of 5 bit size to 32 bit? So if shamt was 11011 it would just be 27 0s and then 11011? If not, what is the correct way to zero extend shamt?

回答1:

One (standard) method is to use ieee.numeric_std and resize(). e.g.:

muxSOut <= std_logic_vector(resize(unsigned(shamt), 32)) ...

One advantage of this is that you can replace 32 with muxSOut'length, and then your code becomes a bit more flexible.

回答2:

I would probably just expect:

muxSOut <= x"000000" & "000" & shamt when muxSSel = '0' else A;