simulation error in verilog

问题:

my code for the design block and the testbench compiles, however when i simulate i'm not getting the correct output. Can anyone tell me where i'm going wrong in my code?

Here is the code for testbench:

module testbench;
reg [511:0]FROM_LS;
reg CLK;
reg [63:0]TO_IF_ID;

initial
 begin
  CLK= 0;
  TO_IF_ID[63:0]=63'b0;
  FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
  FROM_LS[479:448]=32'b00_11000_00100_01111_11111_00011_10000;
 end
always
 begin
  #10 CLK= ~ CLK;
   //FROM_LS[511:448]= ~ FROM_LS[511:448];
  $display("FROM_LS= %b", FROM_LS);
  $display("TO_IF_ID= %b", TO_IF_ID);
 end
endmodule

and here is the code for the design block:

module inst_line_buffer(input wire [511:0]from_LS,
                    input wire clk,
                    output reg [63:0]to_if_id);
parameter mem_size=16;
integer k;    
reg [31:0] ilb[0:mem_size-1];   

initial
 begin
  for (k = 0; k < mem_size ; k = k + 1)
    begin
    ilb[k] = 32'b00;
    //$display ("ilb= %b",ilb[k]);
    end
 end
 always @(posedge clk)
   begin
   ilb[0]= from_LS[511:480];
   ilb[1]= from_LS[479:448];
   ilb[2]= from_LS[447:416];
   ilb[3]= from_LS[415:384];
   ilb[4]= from_LS[383:352];
   ilb[5]= from_LS[351:320];
   ilb[6]= from_LS[319:288];
   ilb[7]= from_LS[287:256];
   ilb[8]= from_LS[255:224];
   ilb[9]= from_LS[223:192];
   ilb[10]= from_LS[191:160];
   ilb[11]= from_LS[159:128];
   ilb[12]= from_LS[127:96];
   ilb[13]= from_LS[95:64];
   ilb[14]= from_LS[63:32];
   ilb[15]= from_LS[31:00];
   to_if_id [63:32]= ilb[0];
   to_if_id [31:0]= ilb[1];
   $display("ilb= %b", ilb[1]);
  end
endmodule

i'm expecting that the value of TO_IF_ID should be 0001100000001000110011100101110100110000010001111111110001110000 but i;'m getting all zeros. Can anyone help me out?

回答1:

When you run a simulation on your testbench module, TO_IF_ID is always 0 because you only assigned a value to it once at time 0 in your initial block. If you want the value to change, it needs to be driven somehow.

As Andy pointed out in a comment, you probably meant to instantiate the inst_line_buffer module in your testbench. Verilog will not do this magically for you. But then, you should declare TO_IF_ID as a wire instead of a reg and remove it from the initial block.

module testbench;
reg [511:0]FROM_LS;
reg CLK;
wire [63:0]TO_IF_ID;

inst_line_buffer inst_line_buffer (
    .from_LS    (FROM_LS),
    .clk        (CLK),
    .to_if_id   (TO_IF_ID)
);

initial begin
  CLK= 0;
  FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
  FROM_LS[479:448]=32'b00_11000_00100_01111_11111_00011_10000;
    #500 $finish;
 end
always
 begin
  #10 CLK= ~ CLK;
   //FROM_LS[511:448]= ~ FROM_LS[511:448];
  $display("FROM_LS= %b", FROM_LS);
  $display("TO_IF_ID= %b", TO_IF_ID);
 end
endmodule