I used the following code to instantiate 2-D memory in a verilog
reg [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};
reg [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};
This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done
Can anyone elaborate to me as in how that is possible?
For Altera devices: https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_ram.html
For Xilinx devices (as given by Paebbels): http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf (Chapter 3, "Initializing RAM Contents")
For Lattice devices: http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/EI/iCEcube2_2013-08_userguide.pdf?document_id=50165 ("Initializing Inferred RAM")
For Microsemi devices: http://www.microsemi.com/document-portal/doc_view/129865-ac162-ram-initialization-and-rom-emulation-in-proasic-sup-u-plus-u-sup-devices-app-note
A short search with google and I found this: How to initialize contents of inferred Block RAM (BRAM) in Verilog
Just google it :-)
