How can I share and use just one RAM module in mul

问题:

I want to write a module in RAM and then read from the same into another module. How can I do this? I think there must be a way to pass RAM modules by referencing to other modules. For example:

In module A:

// write in ram and pass to module B

ram ram_ins();
ram_ins.wr_en = 1;
ram_ins.addr = 1;
ram_ins.data_in = 1234;
B b_ins(ram_ins); // pass by reference the ram_ins to the module B 

In module B:

// read from ram 

ram_ins.addr = 1;
reg [7:0] a;
assign a = ram_ins.data_out

Register a in module B must be 1234, because in module A 1234 is written in address 1 of RAM.

回答1:

You can access to RAM from other modules you need some control module for this or communication bus. For example Altera UFM I2C interface. RAM can be write by module A and read by module B with different clocks (Dual-ported RAM):

http://www.asic-world.com/examples/verilog/ram_dp_sr_sw.html

http://www.asic-world.com/examples/verilog/ram_dp_ar_aw.html

At a certain level of abstraction I2C device address is your reference.

Sorry for My English.

回答2:

One Ram cannot be accessed by two different modules. What you need is a module to arbitrate between the accesses I'll just show the write path for simplicity i.e.:

module ram ( 
    input clk,
    input wr,
    input [7:0] data
);
///Ram model here
endmodule

module arbiter (
input clk,
input rst_n,


output ram_wr,
output [7:0] ram_data,

output [1:0] write_accepted,

input m0_wr,
input [7:0] m0_data,
input m1_wr,
input [7:0] m1_data,
);
always @(posedge clk or negedge rst_n)
if (!rst_n) 
  current <= 1'b0;
else
  current <= !current;

assign ram_data = current ? m1_data : m0_data;
assign write_accepted = {(current & m1_wr),(!current & m1_wr)};
assign ram_wr = |write_accepted;
endmodule

So many reasons I wouldn't want to ship a chip with that code in, but hopefully you get the idea.