I found this in systemverilog
:
task automatic xxx(ref xxxpackage bus,input interface ift);
I want to know the usage of ref
. What is the advantage?
I found this in systemverilog
:
task automatic xxx(ref xxxpackage bus,input interface ift);
I want to know the usage of ref
. What is the advantage?
Normally, task and function arguments declared as input
are copied by value upon entry to the routine, and arguments declared as output
are copied by value upon returning from the routine. inout
arguments are copied both upon entry and return from the routine. Arguments declared with ref
are not copied but instead are references to the actual arguments used when making the call to the routine. There are much stricter data type compatibility rules when using ref arguments.
In a task that consumes time, a ref can be used instead of an inout to capture value changes that occur while the task is active. Remember that an inout argument is copied into the task when it is called, and copied out when the task returns. Here is an example that you should try.
module top;
logic A,B;
task automatic mytask(inout logic arg1, ref logic arg2);
#0 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
// actual arguments have been set to 0
#5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
#0 arg1 = 1; arg2 = 1;
#5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
endtask
initial #1 mytask(A,B);
initial begin
A = 'z; B ='z;
#2 A = 0; B = 0; // after call
// arguments have been set to 1
#5 $display("%m %t A %b B %b",$time,A ,B);
#5 $display("%m %t A %b B %b",$time,A ,B);
end
endmodule
See the difference between the inout
and pass by ref
arguments.
Note that a class variable is a reference to a class handle already, so passing a class variable by reference rarely has any benefit. Also, in a function, the only benefit of a ref
argument might be performance in passing large data structures like an array instead of using an input
, output
, or inout
.
A ref argument is a variable passed by reference. This type of argument are not a copy but a reference to the original variable.
Arguments passed by reference are not copied into the subroutine area, rather, a reference to the original argument is passed to the subroutine. The subroutine can then access the argument data via the reference.
From section 13.5.2 in IEEE Std 1800-2012.
Hey bunch here's the explanation of the example that DAVE gave. Thanks a lot for the example Dave.
module top;
logic A,B;
task automatic mytask(inout logic arg1, ref logic arg2);
#0 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
// actual arguments have been set to 0
#5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
#0 arg1 = 1; arg2 = 1;
#5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
endtask
initial #1 mytask(A,B);
initial begin
A = 'z; B ='z;
#2 A = 0; B = 0; // after call
// arguments have been set to 1
#5 $display("%m %t A %b B %b",$time,A ,B);
#5 $display("%m %t A %b B %b",$time,A ,B);
end
endmodule
/*Both the two 'initial' statements are running simultaneously*/
/* 1) At time t=0 A and B are set to z by second initial statement
2) At time t=1 mytask(A,B) is called by first initial
statement,
the first display statements displays arg1 and arg2 =z as
set by A and B.
3) t=3 the second initial statement sets A=0 and B=0, but only
A=0 is passed to arg 1 in the ongoing task since it is
passed by reference, whereas B=0 can only be passed at the
starting or the end of the task since it is passed by value
hence arg2 remains z.
4) inside the task--At t=6 values of arg1 and arg2 are
displayed
5) at t=6 the values of arg1 and arg2 are made 1.
6) in the second initial statement at t=7 values of A and B
is displayed, since arg2 is passed through reference
therefore it becomes 1, whereas A remains zero until the end of
the task.
7) at t=11 the values of arg1 and arg2 are displayed. -- task
ends.
8) Since the task is ended arg2 value is passed to B and is
displayed by the second initial statement at t=12.
*/
I have explained as per the output displayed in the kernel and timing it shows hope this helps.