I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard.
The problem is that it created a write enable signal (wea
) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch:
Line ###: Type error near encnt ; current type std_logic; expected type std_logic_vector
How can I cast encnt
, which is std_logic, to a one bit std_logic_vector?
(ISE doesn't allow me to change wea from the file of memory.)