For example: IOs A and B are connected have a 10ns io-to-io delay between them. The IOs run at 500MHz (2ns period).
By default Verilog uses inertial delay which acts as a filter. Therefore defining the interconnect wire as wire #(10ns) io; will not work since it will filter out the data.
wire #(10ns) io;
assign io = io_a_en ? a_data_500MHz : 'z;
assign io = io_b_en ? b_data_500MHz : 'z;
Transport delay is unidirectional. Creating one for each direction on an IO will cause multiple drivers and a feedback loop.
always @(a) b_reg <= #(10ns) a;
always @(b) a_reg <= #(10ns) b;
assign a = b_reg; // feedback b_reg = b = a_reg = a ... and multi-driver
assign b = a_reg; // feedback a_reg = a = b_reg = b ... and multi-driver
assign a = io_a_en ? a_data_500MHz : 'z;
assign b = io_b_en ? b_data_500MHz : 'z;
How should one model bidirectional transport delay?
Bidirectional transport delay can be achieved using driver strength with the two uni-directional transport delay. The model should assign the nets to a weaker drive strength the the IO drivers. This will give priority to the real driver and prevent driver conflict.
To prevent a feedback loop, use the drive strength as the qualifier to decide if the transport delay should assign the source value or high-Z. An easy way to determine the drive strength is with with %v, see IEEE Std 1800-2012 § 21.2.1.5 Strength format
module bidi_delay #( parameter INERTIAL=0, TRANSPORT=10 ) (
inout a, b
);
reg a2b, b2a;
reg [23:0] a_strength, b_strength;
always @(a) begin
$sformat(a_strength, "%v", a);
a2b <= #(TRANSPORT) (a_strength[23:16] == "S") ? a : 1'bz;
end
always @(b) begin
$sformat(b_strength, "%v", b);
b2a <= #(TRANSPORT) (b_strength[23:16] == "S") ? b : 1'bz;
end
assign (weak0,weak1) #(INERTIAL) a = b2a;
assign (weak0,weak1) #(INERTIAL) b = a2b;
endmodule
Tested on EDAplayground with Aldec Riviera, Icarus Verilog, and GPL Cver
