QuartusII Synthesis: Enumerated type to State sign

I am designing an FSM in SystemVerilog for synthesis through the QuartusII (14.1) tool to put on an Altera FPGA. I am using an enum declaration to make the code much more reasonable:

typedef enum logic [7:0] { CMD_INIT,
                           CMD_WAIT,
                           CMD_DECODE,
                           CMD_ILLEGAL,
                           CMD_CMD0,
                           ... } cmd_st;
...
cmd_st cs, ncs;
...

Whenever Quartus synthesized this state machine, it seems to create a one-hot encoding despite the logic [7:0] part of the type. As in, when I got to add the states to SignalTap, I get all of the states as a signal 1-bit variable (cs.CMD_INIT, cs.CMD_WAIT, etc). While this is usually pretty useful, as I need to see a bunch of these states and some over values at once, I am running out of on-chip memory to contain all of these states (there are well over 8 of them; like 50+). So adding all of them to SignalTap takes ALOT of this memory; but if I could just put down the 8-bit value for cs, I would have plenty of space for other things.

I cant figure out how to get Quartus to NOT use the 1-hot encoding for the FSM. I have tried changing the settings (Settings->Compiler Settings->Advance Settings (Synthesis...)->State Machine Processing) to Minial Bits, User Encoding and Sequential, as well as added values for a few of the states:

typedef enum logic [7:0] { CMD_INIT           = 8'd0,
                           CMD_WAIT           = 8'd1,
                           CMD_DECODE         = 8'd2,
                           CMD_ILLEGAL        = 8'd3,
                           CMD_CMD0,

(Note, not all of them as there are a bunch of I might add even more in the middle)

Im not sure what else to do so that SignalTap sees only 8-bits for the states (which probably goes back to getting Quartus to synthesize this FSM as sequential rather than 1hot encoding)

You can use synthesis pragmas to guide Quartus to use a specific encoding scheme for the state variables. This page gives you details on how to encode state machines using "sequential" encoding thereby avoiding the default one-hot encoding.