Directly indexing a bit of an arithmetic result

2019-08-04 14:59发布

问题:

For this issue, consider that I have the following signals and am using The Synopsis packages std_logic_unsigned and std_logic_arith.

signal o : std_logic;
signal i  : std_logic_vector(parameter downto 0);
constant c : integer := 5;

I wish to set the o signal to the leftmost bit of the result of (i-c). Inside of a process I have something like:

o <= (i-c)(i'left);

Which does not compile in my simulator.

I know I can solve this by introducing an intermediary variable, but is there a syntactic construct to do this directly?

回答1:

You are trying to assign o the indexed name value from the result of an expression.

A indexed name prefix can be either a name or a function call.

 indexed_name ::=  prefix ( expression { , expression } )

 prefix ::=  
       name
     | function_call

Functions are expressions as are most predefined attributes, e.g. i'length or i'left.

A function call however has a specific format:

 function_call ::=
    function_name [ ( actual_parameter_part ) ]

 actual_parameter_part ::=  parameter_association_list 

Keeping all that in mind as well as using package numeric_std (in this case without numeric_std_unsigned) gives:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity indexing is
    constant parameter: natural :=7;
end entity;

architecture foo of indexing is
    signal o : std_logic;
    signal i  : signed(parameter downto 0);
    constant c : integer := 5;
begin

    o <= "-"(i,to_signed(c,i'length)) (i'left);

end architecture;

And of course you could use type conversions in the association list for the "-" function call association list,

Type signed was selected because your constant c was specified as type integer. It could have easily been type unsigned, or std_logic_vector using package numeric_std_unsigned. Selecting type signed is in part whimsical, o specifies the result sign this way.

The above example analyzes, elaborates and runs, not actually doing much interesting, while demonstrating the syntax is valid.

Slice names can be similarly manipulated.

(And yes this would work with Synopsys's package std_logic_unsigned, without the type conversions and specifying i type std_logic_vector. There's little advantage when using a function call.)



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