CPPUTestMakeFile Help linking

I am trying to make a makefile, which can make an exe for CppUTest. It can not find the headers, what have I done wrong? First time making a makefile, not 100% sure what I'm doing.

#The compiler to use
CC = g++
LINK = -g -pedantic -Wall -lstdc++ -lpthread -ldl -lm -Wl,-rpath,.
COMPILE = -g -O3 -D_THREAD_SAFE -pedantic -Wall -c -Wno-deprecated 
#Name of the EXE file to create.
EXE    = ./Tests
SRCS   = $(shell ls *.cpp)
OBJS   = $(subst .cpp,.o,$(SRCS))
#Extra flags to give to the C compiler.
CFLAGS = 
#Libraries to include
LIBS= -lCppUTestExt -lCppUTest -lm 
#Extra flags to give to the C++ compiler. 
CXXFLAGS = -I/home/mg/DS-5-Workspace/Tests/include       
#Extra flags to give to compilers when they are supposed to invoke the linker, ‘ld’, 
#such as -L. Libraries (-lfoo) should be added to the LDLIBS variable   
#instead.            

LDFLAGS = -L/home/mg/DS-5-Workspace/Tests/cpputest/lib
#Extra flags to give to the C preprocessor and programs that use it (the C and  
#Fortran     compilers). 

CPPFLAGS = 

.SUFFIXES: .o .cpp

.cpp.o:
$(CC) $(CFLAGS) $(CXXFLAGS) $(LDFLAGS) $(COMPILE) $(LIBS) $<

all: $(OBJS)
$(CC) $(CFLAGS) $(CXXFLAGS) $(LDFLAGS) $(LIBS) $(OBJS) -o $(EXE) $(LINK)


-include depend.mak


depend:
g++ -MM $(SRCS) > depend.mak


#static:
#ar -crvs $(a) $(OBJS)


#shared: $(OBJS)
#$(CC) -shared -Wl,-soname -lc -o $(so) $(OBJS) 

clean:
rm -rf $(OBJS) depend.mak $(EXE) $(so) $(a)

I have the following error:

error: CppUTest/CommandLineTestRunner.h: No such file or directory

Well, you're mixing up a lot of things.

Let's clean this up and keep only what is needed :

EXE         :=  Tests

SRC         :=  $(wildcard *.cpp)

OBJ         :=  $(SRC:%.cpp=obj/%.o)

DEP         :=  $(OBJ:.o=.d)

LDLIBS      :=  -lCppUTestExt -lCppUTest -lm -lstdc++ -lpthread -ldl

LDFLAGS     :=  -L/home/mg/DS-5-Workspace/Tests/cpputest/lib
LDFLAGS     +=  -Wl,-rpath,.

CPPFLAGS    :=  -I/home/mg/DS-5-Workspace/Tests/include
CPPFLAGS    +=  -MMD -MP -D_THREAD_SAFE

CXXFLAGS    :=  -W -Wall -Wno-deprecated -pedantic -O3 -g

.PHONY: all clean fclean re

all:    obj $(EXE)

clean:
    $(RM) -r obj

fclean: clean
    $(RM) $(EXE)

re: fclean all

-include $(DEP)

$(EXE): $(OBJ)
    $(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $@

# %.a:  $(OBJ)
#   $(AR) crvs $@ $^
#   ranlib $@

# %.so: CXXFLAGS += -fPIC
# %.so: $(OBJ)
#   $(CXX) $(LDFLAGS) $^ $(LDLIBS) -o $@

obj:
    @mkdir -p $@

obj/%.o:    %.cpp
    $(CXX) $(CPPFLAGS) $(CXXFLAGS) -o $@ -c $<

Some explanations :

Avoid the $(shell ...) function, because it'll be executed each time the variable is called if assigned with the = operator instead of := operator.
$(CC) is a built-in variable containing cc or gcc (should be equivalent). Use the built-in $(CXX) to use g++.
-g, -pedantic, -O3, -Wno-deprecated and -Wall are compiler flags, they should be in the CFLAGS (for C) or CXXFLAGS (for C++) built-in variables.
-I <path> and -D_THREAD_SAFE are preprocessor flag, thus should be in the CPPFLAGS built-in variable.
-MMD -MP will auto-generate dependency files (.d extension) for each .o file. You can read more here.
.cpp.o: is a suffix rule, and suffix rules are the old-fashioned way of defining implicit rules for make. You should just rely upon these implicit rules make already know about or make your own the modern way.
You don't need to define .SUFFIXES: by yourself for such widely used targets. The variable SUFFIXES is defined to the default list of suffixes before make reads any makefiles. Make 3.82 defines these suffixes by default :
```
.SUFFIXES: .out .a .ln .o .c .cc .C .cpp .p .f .F .m .r .y .l .ym .yl .s .S .mod .sym .def .h .info .dvi .tex .texinfo .texi .txinfo .w .ch .web .sh .elc .el
```