VHDL - ror and rol operations

How can I solve this problem? reg variable is defined as:

 signal reg:STD_LOGIC_VECTOR(7 downto 0):="00000001";

There is a problem with ror operation in the code below. The error message is:

Line 109: Syntax error near "ror".

Line 108: found '0' definitions of operator "=", cannot determine exact overloaded matching definition for "="

  process(clk1,up_down,enable,reset)
        begin
        if up_down="1" then
            reg ror 1;
        end if;
        end process;

Your problem is the the ror operator is not defined for std_logic_vector.

VHDL exhibits a behaviour of computer (and hardware description) languages called overloading. Overloading is where an operator, function or procedure is multiply defined for different types. The compiler looks at the combination of types when the operator (etc) is used (called the signature) and tries it match that with the various versions that have been declared. This only works if there is exactly one match. Any more and the code is ambiguous, because the compiler doesn't know which version to used. Any less and there is no version for the compiler to use. This is your problem - there is no version of the ror operator that uses std_logic_vector.

You have two solutions:

(i) RECOMMENDED : implement your rotate right behaviour manually using the concatenation operator and slicing:

    if up_down="1" then
        reg <= reg(0) & reg(7 downto 1);
    end if;

(ii) NOT RECOMMENDED : convert your std_logic_vector to a different type that does have a version of the ror operator defined, eg unsigned. Why "not recommended"? Because I would not recommend using any the the following operators ever, because they can behave strangely (and their behaviour doesn't seem to be consistent across different EDA tools);