Can't compile VHDL package - Modelsim error: (

Quite a simple one, but I am pulling my hair out and need some fresh eyes. The problem is detailed below, originally I had the issue with a much larger package containing multiple items so stripped everything back to basics and still can't work it out...

thanks in advance

Simple code:

----------------------------------
--  LIBRARY_DECLARATIONS
----------------------------------
library STD;
use     STD.standard.all;
----------------------------------
library IEEE;
use     IEEE.std_logic_1164.all;
----------------------------------
--  PACKAGE_DECLARATION
----------------------------------
package Dummy_pkg is

   component dummy_comp is
      (
         SIG_IN  : in    std_logic;
         SIG_BI  : inout std_logic;
         SIG_OUT : out   std_logic
      );
   end component dummy_comp;

end package TB_PHAS_FPGA_DUT_pkg;

package body TB_PHAS_FPGA_DUT_pkg is
end package body TB_PHAS_FPGA_DUT_pkg;

And this is the error I am getting from Modelsim (MS version):

vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd
# Model Technology ModelSim Microsemi vcom 10.5c Compiler 2016.07 Jul 21 2016
# Start time: 13:49:21 on Oct 11,2018
# vcom -reportprogress 300 -work work C:/_WorkDir/pkg_issue/Dummy_pkg.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package Dummy_pkg
# ** Error: C:/_WorkDir/pkg_issue/Dummy_pkg.vhd(20): near "(": (vcom-1576) expecting END.
# End time: 13:49:21 on Oct 11,2018, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0

回答1:

You meant:

   component dummy_comp is
      port                           --  <--------------------
      (
         SIG_IN  : in    std_logic;
         SIG_BI  : inout std_logic;
         SIG_OUT : out   std_logic
      );
   end component dummy_comp;

回答2:

Got it - I am missing 'port' from the component declaration.... always after you post... typical... sorry to waste time.
rgds, g.