Full 8 bit adder, illogical output

问题:

I have created an 8 bit adder with a fulladder. As you can see, i started adding the bits from the right to left with the corresponding bits and for cin the signals t1 and t2 and cout the t2 and t1 in order. The first cin is set to the adder input cin. I don't see any problems in my implementation, but when i run it, i get red line for the o output signal.Can somebody tell me what is going wrong?(i have tested the fulladder and returns the right results.)

Thank you.

Here is the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder8bit is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           cin : in  STD_LOGIC;
           o : out  STD_LOGIC_VECTOR (7 downto 0);
           cout : out  STD_LOGIC);
end adder8bit;

architecture Behavioral of adder8bit is

component fulladder is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           o : out  STD_LOGIC;
           cout : out  STD_LOGIC);
end component;

signal t1,t2:std_logic:='0';

begin

C1: fulladder port map( a => a(0), b => b(0), cin => cin, o => o(0), cout => t1 );
C2: fulladder port map( a => a(1), b => b(1), cin => t1, o => o(1), cout => t2 );
C3: fulladder port map( a => a(2), b => b(2), cin => t2, o => o(2), cout => t1 );
C4: fulladder port map( a => a(3), b => b(3), cin => t1, o => o(3), cout => t2 );
C5: fulladder port map( a => a(4), b => b(4), cin => t2, o => o(4), cout => t1 );
C6: fulladder port map( a => a(5), b => b(5), cin => t1, o => o(5), cout => t2 );
C7: fulladder port map( a => a(6), b => b(6), cin => t2, o => o(6), cout => t1 );
C8: fulladder port map( a => a(7), b => b(7), cin => t1, o => o(7), cout => cout );

end Behavioral;

回答1:

It appears to me, that you assume that your instances C1 ... C8 are executed sequentially and therefore you alternate the two signals t1 and t2 as if this was a program where variables can be reused.

However you are creating a structure with connections here and t1 will be the same signal for all 8 instances on which you are using it. Therefore you have 4 drivers C1, C3, C5 and C7 for t1 (and similarly for t2) and this code would most likely not be synthesizable.

What you could do is use 8 carry signals in a setup as follows:

signal c: std_logic_vector(7 downto 1) := (others => '0');
-- ...
C1: fulladder port map( a => a(0), b => b(0), cin => cin, o => o(0), cout => c(1) );
C2: fulladder port map( a => a(1), b => b(1), cin => c(1), o => o(1), cout => c(2) );
C3: fulladder port map( a => a(2), b => b(2), cin => c(2), o => o(2), cout => c(3) );
-- ...
C8: fulladder port map( a => a(7), b => b(7), cin => c(7), o => o(7), cout => cout );

Furthermore you could have a look at foor-generate-loops to reduce the amount of repetition in your code. If you extend the carry-vector to include cin and cout, all 8 lines then look the same (except for the increasing indices).

signal c: std_logic_vector(8 downto 0) := (others => '0');
-- ...
c(0) <= cin;
cout <= c(8);
-- ...
-- your for-generate loop here...

回答2:

Probably your signals t1 and t2 should be of type std_logic_vector instead of std_logic.