Verilog: on left-hand side of assignment must have

问题:

I am having trouble with combination assignment. I do not understand why I cannot use a always combination structure the set my output variables. When I use assign, I do not get the assignment error.

I thought assign and always@(*) both means blocking (combinational assignment)

module control_unit(input wire [31:0] instruction
                   ,output wire RegDst
                   ,output wire ALUSrc
                   ,output wire RegWrite
                   ,output wire MemRead
                   ,output wire MemWrite
                   ,output wire MemToReg
                   ,output wire Branch
                   );

   wire [5:0] opcode;

   assign opcode  = instruction[31:26];

   always@(*) begin
      case(opcode)
            6'b000000: begin              // r-type
               RegDst   = 1'b1;
               ALUSrc   = 1'b0;
               RegWrite = 1'b1;
               MemRead  = 1'b0;
               MemWrite = 1'b0;
               MemToReg = 1'b0;
               Branch   = 1'b0;
            end
           .
           .
           .                    
            default: begin
               RegDst   = 1'b0;
               ALUSrc   = 1'b0;
               RegWrite = 1'b0;
               MemRead  = 1'b0;
               MemWrite = 1'b0;
               MemToReg = 1'b0;
               Branch   = 1'b0;
            end
      endcase
   end // end always_comb
endmodule

回答1:

You cannot make a procedural assignment to a wire. You must make a procedural assignment to a reg, regardless of whether the always block describes sequential or combinational logic. Use the following port declarations:

               ,output reg RegDst
               ,output reg ALUSrc
               ,output reg RegWrite
               ,output reg MemRead
               ,output reg MemWrite
               ,output reg MemToReg
               ,output reg Branch