I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows:
library ieee;
use ieee.std_logic_1164.all;
entity vivado_rtl_island is
port(
-- Clocks
i_m50_clk :in std_logic;
i_m50_rst :in std_logic;
-- APB Command Inteface
s_paddr :in std_logic_vector(31 downto 0);
s_psel :in std_logic;
s_penable :in std_logic;
s_pwrite :in std_logic;
s_pwdata :in std_logic_vector(31 downto 0);
s_pready :out std_logic;
s_prdata :out std_logic_vector(31 downto 0);
s_pread :out std_logic;
s_pslverr :out std_logic
);
end entity;
architecture rtl of vivado_rtl_island is
-- Define APB Interface for "Vivado IP Integrator"
ATTRIBUTE X_INTERFACE_INFO: STRING;
ATTRIBUTE X_INTERFACE_INFO of s_paddr: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PADDR";
ATTRIBUTE X_INTERFACE_INFO of s_psel: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSEL";
ATTRIBUTE X_INTERFACE_INFO of s_penable: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PENABLE";
ATTRIBUTE X_INTERFACE_INFO of s_pwrite: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWRITE";
ATTRIBUTE X_INTERFACE_INFO of s_pwdata: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PWDATA";
ATTRIBUTE X_INTERFACE_INFO of s_pready: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PREADY";
ATTRIBUTE X_INTERFACE_INFO of s_prdata: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PRDATA";
ATTRIBUTE X_INTERFACE_INFO of s_pslverr: SIGNAL is "xilinx.com:interface:apb:1.0 APB_S PSLVERR";
begin
end architecture;
There I try to compile the above rtl using GHDL as follows:
$ ghdl -a --std=08 --ieee=synopsys --work=work vivado_rtl_island.vhd
GHDL produces the following error:
vivado_rtl_island.vhd:28:33: no "s_paddr" for attribute specification
vivado_rtl_island.vhd:29:33: no "s_psel" for attribute specification
vivado_rtl_island.vhd:30:33: no "s_penable" for attribute specification
vivado_rtl_island.vhd:31:33: no "s_pwrite" for attribute specification
vivado_rtl_island.vhd:32:33: no "s_pwdata" for attribute specification
vivado_rtl_island.vhd:33:33: no "s_pready" for attribute specification
vivado_rtl_island.vhd:34:33: no "s_prdata" for attribute specification
vivado_rtl_island.vhd:35:33: no "s_pslverr" for attribute specification
However, when I compile this with modelsim, it doesn't produce an error.
Does anybody know how to work around this problem in GHDL so that I can add these attributes and the simulator will ignore them and not produce and error?
See IEEE Std 1076-2008 7.2 Attribute specification, paragraph 9:
An attribute specification for an attribute of an entity declaration, an architecture, a configuration, or a package shall appear immediately within the declarative part of that declaration. Similarly, an attribute specification for an attribute of an interface object of a design unit, subprogram, block statement, or package shall appear immediately within the declarative part of that design unit, subprogram, block statement, or package. Similarly, an attribute specification for an attribute of an interface object of a design unit, subprogram, block statement, or package shall appear immediately within the declarative part of that design unit, subprogram, block statement, or package. ...
The design unit is the entity declaration (3.2 Entity declarations), a primary unit (13.1 Design units). This semantic restriction has been in place in every IEEE Std 1076 revision (-1987 through -2008, prior to -2008 found in 5.2 Attribute specification). Modelsim is wrong to 'compile' your specifications.
Xilinx's Vivado synthesis historically takes advantage of the Modelsim behavior. What's funny here is Vivado inconsistently adheres to the semantic requirement of the first quoted sentence of 7.2 above which is also found in earlier revisions but not the second. You can declare an attribute on an entity in the entity declarative part while Vivado at least historically required specify attributes on ports in the architecture declarative part.
All isn't lost when using ghdl. There's a command line argument that can be passed during analysis to relax various rules to match Modelsim's behavior where relied on by third party tools.
ghdl -a --std=08 --ieee=synopsys -frelaxed-rules --work=work vivado_rtl_island.vhdl
vivado_rtl_island.vhdl:28:33:warning: attribute for port "s_paddr" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:29:33:warning: attribute for port "s_psel" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:30:33:warning: attribute for port "s_penable" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:31:33:warning: attribute for port "s_pwrite" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:32:33:warning: attribute for port "s_pwdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:33:33:warning: attribute for port "s_pready" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:34:33:warning: attribute for port "s_prdata" must be specified in the entity [-Wspecs]
vivado_rtl_island.vhdl:35:33:warning: attribute for port "s_pslverr" must be specified in the entity [-Wspecs]
You can add the command line flag -frelaxed-rules and the errors will be converted to warnings.
The default ghdl behavior is changed for standard revision -2008. You'd note that without specifying --std=08 the default standard compliance is --std=93c which includes -frelaxed-rules and is otherwise compatible with `--std=93 (-1993). There isn't a -2008 revision with relaxed rules included.
The reason behind the semantic restriction would stem from a leading (at the time -1987) vendor not being able to implement specifying a user attribute on a port without having direct access to the port declaration. While that vendor is likely no longer providing VHDL products the restriction remains.
We find various instances of of Modelsim effectively trying to steer the standard by market share influence (they have a command line -pendanticerrors argument changing a lot of warnings to errors).
ghdl development follows their lead with the exception that strict compliance with the standard is the norm (--std=93c as a default notwithstanding) with command line arguments enabling warnings instead of errors.
The reasoning for this would be that those implementing VHDL tend to do so from the standard and not by reverse engineering the vendor with the greatest market share.
The -frelaxed-rules description may not be complete in ghdl documentation. Mention is found in the sections on VHDL standards as well as other sections.
Xilinx has been made aware of the issue. Modelsim undoubtedly knows where they vary from the standard and there currently is no vendor participation in the VHDL standard revision process.
Looking through the ghdl source tree ghdl-0.35 was released on Dec 14, 2017, and Issue 525 had a fix on Feb 7, 2018 (see src/vhdl/sem_specs.adb) to add port attributes to the architecture declarative part with -frelaxed-rules to provide the present functionality regardless of --std=08 (during the ghdl-0.36 developement cycle).
Also see Issue 838 Xilinx Vivado and Modelsim support attributes on ports differently than GHDL, on github wherein the OP sought a second opinion stating this answer is valid.
You are using VHDL2008, apparently.
With VHDL 2008, entity port attributes must go into the entity definition, i.e. you need to move your attributes before the end entity statement.
Compile like this with GHDL:
ghdl.exe -a -frelaxed-rules --std=08 --ieee=synopsys --work=work ./vivado_rtl_island.vhd
And move port attributes to Architecture block...
then it will work consistently with both Xilinx Vivado and GHDL.
