Using Regular Expressions for Verilog Port Mapping

问题:

I have a really long port map where I want to replace a bunch of

SignalName[i],

with

.SignalName(SignalName[i]),

I think I can do this easily with regular expressions, but I can't for the life of me figure out how. Any ideas?

回答1:

Assuming SignalData is the file containing your port map information, the following would do what you want.

sed -si 's/\([a-zA-Z]\+\)\(\[[^\]]*\]\)/\.\1(\1\2)/g' SignalData

In sed s stands for substitution, regex between the first pair of // is used to match against each line. If a match is found the expression between upto the next / is made to replace what was matched.

Explanation of regex

\([a-zA-Z]\+\) - Matches a series of alphabets (like SignalName) and captures it into
\1. If you want only the SignalName string to match, replace [a-zA-Z]\+ with SignalName.
\(\[[^\]]*\]\) - Matches the [some character] part and captures it into \2

Finally we use these captured strings to construct the desired string.

If you want to experiment with this before running on your file use sed -s instead of sed -si. That will show the results of the transformation on stdout, without actually changing the file

回答2:

Chiming in 3 years late, but I highly recommend verilog mode for emacs. It simplifies this kind of operation for instantiating modules. For example, if you have a module like this:

module submodule(
  input [1:0] ina,
  input inb,
  input inc,
  output outa);

  /*some stuff*/

endmodule

You can instantiate this using verilog mode:

module mymodule(
  /*AUTOOUTPUT*/
  /*AUTOINPUT*/);

  submodule submod(/*AUTOINST*/);

endmodule

When you expand AUTOs in emacs (C-c C-a), you get this:

module mymodule(
  input [1:0] ina,
  input inb,
  input inc,
  output outa);

  submodule submod(
    .ina    (ina),
    .inb    (inb),
    .inc    (inc),
    .outa   (outa));

endmodule

You can expand this with simplified regular expressions and lisp equations to do complex connections. Saves a ton of time when wiring together a bunch of modules or changing signal names through the hierarchy.

Much more info here: http://www.veripool.org/wiki/verilog-mode/Verilog-mode_veritedium