verilog driving signals on the same wire

问题:

I looked through internet and couldn't find a clear and concise answer to my question. I want to know what'll happen if I drive same strength signals onto the same wire, one of them being logic 1 and the other being logic 0? What do I do if I want a signal to "win", for lack of a better word, depending on the situation?

回答1:

Based on your comment, it sounds like you want a three-state bus. The basic structure to drive a three-state bus is:

assign bus = enable ? out : 1'bz;

Each module driving the bus has a driver of this form. Only one module may have its enable asserted at any time; the bus protocol should define how ownership of the bus is decided. For example, serial buses like I2C have a "master" and a "slave"; the master always talks first, and the slave only talks after it has been requested to by the master.

If you don't want the bus to float when nothing is driving (in simulation, this shows up as a Z value), you can declare the bus as tri0 or tri1 rather than a regular wire.

If multiple modules have the enable asserted at the same time, or if you have multiple standard assign bus = out; drivers attempting to drive different values on the bus, it is known as "contention". This will show up as an X value in simulation, and could result in damage to the drivers in a physical device.

回答2:

I want to know what'll happen if I drive same strength signals onto the same wire, one of them being logic 1 and the other being logic 0?

If the load is a simple net it will be assigned StX(Strong X).

What do I do if I want a signal to "win", for lack of a better word, depending on the situation?

Are you asking how to model this in Verilog or how to do this with MOS devices?