Hi I am trying to use a phased lock loop for clock generation for a VGA controller. I had no luck and decided to make my own clock which then worked fine. I got the VGA controller working. Going back to PLL's though I still can't get a PLL selected to give me an output. I have made a little test model to simulate it.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY PLL4 IS
PORT (
clk : IN std_logic;
a : IN std_logic;
rst : IN std_logic:='0';
x : OUT std_logic
);
END ENTITY PLL4;
ARCHITECTURE A1 OF PLL4 IS
COMPONENT PLL_4 IS
PORT(
clk_in_clk : in std_logic; -- clk
rst_reset : in std_logic; -- reset
clk_out_clk : out std_logic -- clk
);
END COMPONENT PLL_4;
SIGNAL clk25 : std_logic;
BEGIN
CLK_25 : PLL_4 PORT MAP (clk,rst,clk25);
x <= a and clk25;
END ARCHITECTURE A1;
When I simulate this with mod sim I just get the following
I never see the PLL clock output. Can anyone give me some advice on this.
--Update-- After adding the signals from the CLK_25 : PLL I now get the following on Modsim. The rst connects through to the instantiation fine as well a clk to clk_in_clk, but the value clk_out_clk ever changes. See below:
This makes me think the problem I'm having is with the PLL model created with Qsys.The model contained in the .vhd generated by Qsys is below:
-- PLL_4.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.02.09.16:46:16
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity PLL_4 is
port (
clk_in_clk : in std_logic := '0'; -- clk_in.clk
rst_reset : in std_logic := '0'; -- rst.reset
clk_out_clk : out std_logic -- clk_out.clk
);
end entity PLL_4;
architecture rtl of PLL_4 is
component PLL_4_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component PLL_4_altpll_0;
begin
altpll_0 : component PLL_4_altpll_0
port map (
clk => clk_in_clk, -- inclk_interface.clk
reset => rst_reset, -- inclk_interface_reset.reset
read => open, -- pll_slave.read
write => open, -- .write
address => open, -- .address
readdata => open, -- .readdata
writedata => open, -- .writedata
c0 => clk_out_clk, -- c0.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
end architecture rtl; -- of PLL_4