I have a quick question.
How can I use the outputs of two other modules with a new module?
Example:
module test1(ans, X, Y)
output ans;
input X, Y;
do stuff
endmodule
module test2(ans2, X, Y)
output ans2;
input X, Y;
do stuff
endmodule
module result(final_ans, ans, ans2) <------- this is what I mean.
do stuff
endmodule
How would I go about this? How do I call
the other two modules?
Thank you for the help.
You do not call modules. You instance modules. Verilog is not like normal programming languages, it is a hardware simulation language. If you stick to a subset of the language and you use that in the right way that language can also be converted to real hardware. That latter is called RTL (Register Transfer Language). I strongly suggest you find some existing Verilog code examples and study how people use it.
Thus what you do is you make an instance of each module and you connect
signals to the inputs and outputs. Compare it to placing an IC on a board and soldering wires to it. But then all in software.
test1 instance_of_test1 (
.X(signal_into_X),
.Y(signal_into_Y),
.ans(signal_outof_ans)
);
Then you can use the signals coming out of test1 and test2 to go into result:
result instance_of_result (
.ans(signal_outof_ans),
.ans2(signal_outof_ans2),
.final_ans(signal_outof_final_ans)
);
Just as a side note:
The example I use also shows that naming conventions using the port direction is general a bad idea. Signals come out of one module and go into another. Thus the name signal_outof_ans is fine for the module test1 but it is wrong for the module result as there it goes into the module. Here I wanted to emphasize what happens at the level of module test1. (I also know that some companies even prescribe it as the preferred coding style so I am waiting for the flak to arrive on this). In my own code I would never use this. So here is the correct way to code:
wire ans,ans2;
test1 instance_of_test1 (
.X(X),
.Y(Y),
.ans(ans)
);
...
...
result instance_of_result (
.ans(ans),
.ans2(ans2),
.final_ans(final_ans)
);